Datasheet

i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018
66 NXP Semiconductors
Electrical Characteristics
Figure 27. Read Data Latch Cycle Timing Diagram (Non-EDO Mode)
Figure 28. Read Data Latch Cycle Timing Diagram (EDO Mode)
Table 44. Asynchronous Mode Timing Parameters
1
ID Parameter Symbol
Timing
T = GPMI Clock Cycle
Unit
Min Max
NF1 NAND_CLE setup time tCLS (AS + DS) × T - 0.12 [see
2,3
]ns
NF2 NAND_CLE hold time tCLH DH × T - 0.72 [see
2
]ns
NF3 NAND_CEx_B setup time tCS (AS + DS + 1) × T [see
3,2
]ns
NF4 NAND_CEx_B hold time tCH (DH+1) × T - 1 [see
2
]ns
NF5 NAND_WE_B pulse width tWP DS × T [see
2
]ns
NF6 NAND_ALE setup time tALS (AS + DS) × T - 0.49 [see
3,2
]ns
NF7 NAND_ALE hold time tALH (DH × T - 0.42 [see
2
]ns
NF8 Data setup time tDS DS × T - 0.26 [see
2
]ns
NF9 Data hold time tDH DH × T - 1.37 [see
2
]ns
NF10 Write cycle time tWC (DS + DH) × T [see
2
]ns
NF11 NAND_WE_B hold time tWH DH × T [see
2
]ns
NF12 Ready to NAND_RE_B low tRR
4
(AS + 2) × T [see
3,2
]—ns
NF13 NAND_RE_B pulse width tRP DS × T [see
2
]ns
NF14 READ cycle time tRC (DS + DH) × T [see
2
]ns
NF15 NAND_RE_B high hold time tREH DH × T [see
2
]ns
Data from NF
NF14
NF15
NF17
NF16
NF12
NF13
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Data from NF
NF14
NF15
NF17
NF16
NF12
NF13
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