Datasheet

i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018

56 NXP Semiconductors

Electrical Characteristics

WE4 Clock rise to address valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns

WE5 Clock rise to address invalid 0.5

× t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns

WE6 Clock rise to EIM_CSx_B valid -0.5

× t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns

WE7 Clock rise to EIM_CSx_B invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns

WE8 Clock rise to EIM_WE_B valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns

WE9 Clock rise to EIM_WE_B invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns

WE10 Clock rise to EIM_OE_B valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns

WE11 Clock rise to EIM_OE_B invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns

WE12 Clock rise to EIM_EBx_B valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns

WE13 Clock rise to EIM_EBx_B invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns

WE14 Clock rise to EIM_LBA_B valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns

WE15 Clock rise to EIM_LBA_B invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns

WE16 Clock rise to output data valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns

WE17 Clock rise to output data invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns

WE18 Input data setup time to clock rise 2.3 — ns

WE19 Input data hold time from clock rise 2 — ns

WE20 EIM_WAIT_B setup time to clock rise 2 — ns

WE21 EIM_WAIT_B hold time from clock rise 2 — ns

k represents register setting BCD value.

t is clock period (1/Freq). For 104 MHz, t = 9.165 ns.

Table 41. EIM Bus Timing Parameters (continued)

ID Parameter Min

Max

Unit