Datasheet

i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018
48 NXP Semiconductors
Electrical Characteristics
Figure 7. Differential MLB Driver Transition Time Waveform
A 4-stage pipeline is used in the MLB 6-pin implementation to facilitate design, maximize throughput, and
allow for reasonable PCB trace lengths. Each cycle is one ipp_clk_in* (internal clock from MLB PLL)
clock period. Cycles 2, 3, and 4 are MLB PHY related. Cycle 2 includes clock-to-output delay of
Signal/Data sampling flip-flop and Transmitter, Cycle 3 includes clock-to-output delay of Signal/Data
clocked receiver, Cycle 4 includes clock-to-output delay of Signal/Data sampling flip-flop.
MLB 6-pin pipeline diagram is shown in Figure 8.
Figure 8. MLB 6-Pin Pipeline Diagram
Table 33 shows the AC parameters for MLB I/O.
Table 33. I/O AC Parameters of MLB PHY
Parameter Symbol Test Condition Min Typ Max Unit
Differential pulse skew
1
1
t
SKD
= | t
PHLD
–t
PLHD
|, is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
t
SKD
Rload = 50 Ω
between padP
and padN
—— 0.1
nsTransition Low to High Time
2
2
Measurement levels are 20-80% from output voltage.
t
TLH
—— 1
Transition High to Low Time t
THL
—— 1
MLB external clock Operating Frequency fclk_ext — — — 102.4 MHz
MLB PLL clock Operating Frequency fclk_pll — — — 307.2 MHz
padp
padn
VDIFF
0V (Differential)
VDIFF = {padp} - {padn}
t
TLH
20%
80%
20%
80%
t
THL
V
OH
V
OL
0V
0V
0V