Datasheet

Electrical Characteristics
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018
NXP Semiconductors 47
4.7.3 LVDS I/O AC Parameters
The differential output transition time waveform is shown in Figure 6.
Figure 6. Differential LVDS Driver Transition Time Waveform
Table 32 shows the AC parameters for LVDS I/O.
4.7.4 MLB 6-Pin I/O AC Parameters
The differential output transition time waveform is shown in Figure 7.
Single output slew rate, measured between
Vol(ac) and Voh(ac)
tsr Driver impedance =
34 Ω
2.5 — 5 V/ns
Skew between pad rise/fall asymmetry +
skew caused by SSN
t
SKD
clk = 533 MHz
——
0.1 ns
1
Note that the JEDEC JESD79_3C specification supersedes any specification in this document.
2
Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac).
3
The typical value of Vix(ac) is expected to be about 0.5 × OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
Table 32. I/O AC Parameters of LVDS Pad
Parameter Symbol Test Condition Min Typ Max Unit
Differential pulse skew
1
1
t
SKD
= | t
PHLD
–t
PLHD
|, is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
t
SKD
Rload = 100 Ω,
Cload = 2 pF
— — 0.25
nsTransition Low to High Time
2
2
Measurement levels are 20–80% from output voltage.
t
TLH
——0.5
Transition High to Low Time
2
t
THL
——0.5
Operating Frequency f — — 600 800 MHz
Offset voltage imbalance Vos — — — 150 mV
Table 31. DDR I/O DDR3/DDR3L Mode AC Parameters
1
(continued)
Parameter Symbol Test Condition Min Typ Max Unit
padp
padn
VDIFF
0V (Differential)
VDIFF = {padp} - {padn}
t
TLH
20%
80%
20%
80%
t
THL
V
OH
V
OL
0V
0V
0V