Datasheet

Electrical Characteristics
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018
NXP Semiconductors 43
4.6.5 LVDS I/O DC Parameters
The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A,
“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.
Table 26 shows the Low Voltage Differential Signaling (LVDS) I/O DC parameters.
4.6.6 MLB 6-Pin I/O DC Parameters
The MLB interface complies with Analog Interface of 6-pin differential Media Local Bus specification
version 4.1. See 6-pin differential MLB specification v4.1, “MediaLB 6-pin interface Electrical
Characteristics” for details.
NOTE
The MLB 6-pin interface does not support speed mode 8192fs.
Table 27 shows the Media Local Bus (MLB) I/O DC parameters.
Termination Voltage Vtt Vtt tracking OVDD/2 0.49 × OVDD 0.51 × OVDD V
Input current (no pull-up/down) Iin Vin = 0 or OVDD -2.9 2.9 μA
Pull-up/pull-down impedance mismatch
MMpupd
—-1010%
240 Ω unit calibration resolution Rres — — 10 Ω
Keeper circuit resistance Rkeep — 105 175 kΩ
1
OVDD – I/O power supply (1.425 V–1.575 V for DDR3 and 1.283 V–1.45 V for DDR3L).
2
Vref – DDR3/DDR3L external reference voltage.
3
The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot (see Table 31).
Table 26. LVDS I/O DC Parameters
Parameter Symbol Test Conditions Min Max Unit
Output Differential Voltage V
OD
Rload=100 Ω between padP and padN 250 450 mV
Output High Voltage V
OH
I
OH
= 0 mA 1.25 1.6
VOutput Low Voltage V
OL
I
OL
= 0 mA 0.9 1.25
Offset Voltage V
OS
— 1.125 1.375
Table 25. DDR3/DDR3L I/O DC Electrical Parameters (continued)
Parameters Symbol Test Conditions Min Max Unit