Datasheet

Electrical Characteristics
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018
NXP Semiconductors 41
4.6.4.1 LPDDR2 Mode I/O DC Parameters
For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported
DDR3/DDR3L/LPDDR2 Configurations.”
The parameters in Table 24 are guaranteed per the operating ranges in Table 6, unless otherwise noted.
Table 23. RGMII I/O 2.5V I/O DC Electrical Parameters
1
1
Input Mode Selection: SW_PAD_CTL_GRP_DDR_TYPE_RGMII = 10 (1.8V Mode)
SW_PAD_CTL_GRP_DDR_TYPE_RGMII = 11 (2.5V Mode).
Parameter Symbol Test Conditions Min Max Units
High-level output voltage
1
V
OH
Ioh= -0.1 mA (DSE=001,010)
Ioh= -1.0 mA (DSE=011,100,101,110,111)
OVDD-0.15
—V
Low-level output voltage
1
V
OL
Iol= 0.1 mA (DSE=001,010)
Iol= 1.0 mA (DSE=011,100,101,110,111)
—0.15V
Input Reference Voltage V
ref
—
0.49xOVDD 0.51xOVDD
V
High-Level input voltage
2, 3
2
Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6
V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must
be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other
methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
3
To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC
level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.
V
IH
—
0.7xOVDD OVDD
V
Low-Level input voltage
2, 3
V
IL
—0
0.3xOVDD
V
Input Hysteresis(OVDD=1.8V) V
HYS_HighVDD
OVDD=1.8V 250 — mV
Input Hysteresis(OVDD=2.5V) V
HYS_HighVDD
OVDD=2.5V 250 — mV
Schmitt trigger VT+
3, 4
4
Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled
(register IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC[HYS]= 0).
V
TH+
—0.5xOVDD—mV
Schmitt trigger VT-
3, 4
V
TH-
— — 0.5xOVDD mV
Pull-up resistor (22 kΩ PU) R
PU_22K
V
in
=0V — 212 μA
Pull-up resistor (22 kΩ PU) R
PU_22K
V
in
=OVDD — 1 μA
Pull-up resistor (47 kΩ PU) R
PU_47K
V
in
=0V — 100 μA
Pull-up resistor (47 kΩ PU) R
PU_47K
V
in
=OVDD — 1 μA
Pull-up resistor (100 kΩ PU) R
PU_100K
V
in
=0V — 48 μA
Pull-up resistor (100 kΩ PU) R
PU_100K
V
in
=OVDD — 1 μA
Pull-down resistor (100 kΩ PD) R
PD_100K
V
in
=OVDD — 48 μA
Pull-down resistor (100 kΩ PD) R
PD_100K
V
in
=0V — 1 μA
Keeper Circuit Resistance R
keep
— 105 165 kΩ
Input current (no pull-up/down) I
in
V
I
= 0,VI = OVDD -2.9 2.9 μA