Datasheet

Electrical Characteristics
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018
NXP Semiconductors 29
STOP_ON • Arm LDO set to 0.9 V
• SoC and PU LDOs set to 1.225 V
• HIGH LDO set to 2.5 V
• PLLs disabled
• DDR is in self refresh
VDD_ARM_IN (1.4 V) 7.5 mA
VDD_SOC_IN (1.4 V) 22 mA
VDD_HIGH_IN (3.0 V) 3.7 mA
Total 52 mW
STOP_OFF • Arm LDO set to 0.9 V
• SoC LDO set to 1.225 V
• PU LDO is power gated
• HIGH LDO set to 2.5 V
• PLLs disabled
• DDR is in self refresh
VDD_ARM_IN (1.4 V) 7.5 mA
VDD_SOC_IN (1.4 V) 13.5 mA
VDD_HIGH_IN (3.0 V) 3.7 mA
Total 41 mW
STANDBY • Arm and PU LDOs are power gated
• SoC LDO is in bypass
• HIGH LDO is set to 2.5 V
• PLLs are disabled
• Low voltage
• Well Bias ON
• Crystal oscillator is enabled
VDD_ARM_IN (0.9 V) 0.1 mA
VDD_SOC_IN (0.9 V) 13 mA
VDD_HIGH_IN (3.0 V) 3.7 mA
Total 22 mW
Deep Sleep Mode
(DSM)
• Arm and PU LDOs are power gated
• SoC LDO is in bypass
• HIGH LDO is set to 2.5 V
• PLLs are disabled
• Low voltage
• Well Bias ON
• Crystal oscillator and bandgap are disabled
VDD_ARM_IN (0.9 V) 0.1 mA
VDD_SOC_IN (0.9 V) 2 mA
VDD_HIGH_IN (3.0 V) 0.5 mA
Total 3.4 mW
SNVS Only • VDD_SNVS_IN powered
• All other supplies off
• SRTC running
VDD_SNVS_IN (2.8V) 41 μA
Total 115 μW
1
The typical values shown here are for information only and are not guaranteed. These values are average values measured
on a worst-case wafer at 25°C.
Table 9. Stop Mode Current and Power Consumption (continued)
Mode Test Conditions Supply Typical
1
Unit