Datasheet

i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018
28 NXP Semiconductors
Electrical Characteristics
4.1.6 Low Power Mode Supply Currents
Table 9 shows the current core consumption (not including I/O) of the i.MX 6Dual/6Quad processors in
selected low power modes.
NVCC_LVDS2P5 — NVCC_LVDS2P5 is connected to
VDD_HIGH_CAP at the board
level. VDD_HIGH_CAP is capable
of handing the current required by
NVCC_LVDS2P5.
MISC
DRAM_VREF — 1 mA
1
The actual maximum current drawn from VDD_HIGH_IN will be as shown plus any additional current drawn from the
VDD_HIGH_CAP outputs, depending upon actual application configuration (for example, NVCC_LVDS_2P5, NVCC_MIPI, or
HDMI, PCIe, and SATA VPH supplies).
2
Under normal operating conditions, the maximum current on VDD_SNVS_IN is shown Table 8. The maximum VDD_SNVS_IN
current may be higher depending on specific operating configurations, such as BOOT_MODE[1:0] not equal to 00, or use of
the Tamper feature. During initial power on, VDD_SNVS_IN can draw up to 1 mA if the supply is capable of sourcing that
current. If less than 1 mA is available, the VDD_SNVS_CAP charge time will increase.
3
This is the maximum current per active USB physical interface.
4
The DRAM power consumption is dependent on several factors such as external signal termination. DRAM power calculators
are typically available from memory vendors which take into account factors such as signal termination.
See the i.MX 6Dual/6Quad Power Consumption Measurement Application Note (AN4509) for examples of DRAM power
consumption during specific use case scenarios.
5
General equation for estimated, maximum power consumption of an IO power supply:
Imax = N x C x V x (0.5 x F)
Where:
N—Number of IO pins supplied by the power line
C—Equivalent external capacitive load
V—IO voltage
(0.5 xF)—Data change rate. Up to 0.5 of the clock rate (F)
In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz.
Table 9. Stop Mode Current and Power Consumption
Mode Test Conditions Supply Typical
1
Unit
WAIT • Arm, SoC, and PU LDOs are set to 1.225 V
• HIGH LDO set to 2.5 V
• Clocks are gated
• DDR is in self refresh
• PLLs are active in bypass (24 MHz)
• Supply voltages remain ON
VDD_ARM_IN (1.4 V) 6 mA
VDD_SOC_IN (1.4 V) 23 mA
VDD_HIGH_IN (3.0 V) 3.7 mA
Total 52 mW
Table 8. Maximum Supply Currents (continued)
Power Supply Conditions
Maximum Current
Unit
Power Virus CoreMark