Datasheet

Revision History
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018
NXP Semiconductors 165
5 09/2017 Rev. 5 changes include the following:
• Changed throughout:
– Changed terminology from “floating” to “not connected”.
– Removed VADC feature from 19mm x 19mm package. Contact NXP sales and marketing with
enablement options.
• Section 1, “Introduction” on page 1: Corrected typo in last sentence of first paragraph “aut1omotive”.
• Section 1.2, “Features” on page 5: Changed Internal/external peripheral item from “LVDS serial ports—
One port up to 165 MPixels/sec…” to: “…—One port up to 170 MPixels/sec…”.
• Table 1, “Example Orderable Part Numbers”: Added part numbers for silicon revision 1.4 with suffix “E”.
• Section 1.3, “Signal Naming Convention” on page 8” and Section 6.1, “Signal Naming Convention”:
changed wording from updated or changed signal naming, to standard signal naming.
• Table 2, “i.MX 6Dual/6Quad Modules List,” on page 11:
– Added bullet to uSDHC row: “Conforms to the SD Host Controller Standard Specification v3.0”
• Section 4, “Electrical Characteristics” on page 20: Changed several references from JESD and JEDEC
standards to cross references to the Section 4.10, “Multi-Mode DDR Controller (MMDC).
• Table 4, “Absolute Maximum Ratings,” on page 21: Multiple changes:
– Core supply voltages: Separated rows by LDO enabled and LDO bypass. For LDO enabled, changed
maximum value from 1.5 to 1.6V.
– Renamed Internal supply voltages to Core supply output voltage (LDO enabled) and changed
maximum value from 1.3 to 1.4V. Added symbol NVCC_PLL_OUT.
– Reordered VDD_HIGH_IN row and changed maximum value from 3.6 to 3.7V.
– DDR I/O supply voltage row changes:
— Changed Symbols from “Supplies denoted as I/O supply” to: “NVCC_DRAM”
— Added footnote.
– GPIO I/O supply voltage: Added symbols. Changed maximum value from 3.6 to 3.7V.
– Resequenced: HDMI, PCIe, and SATA PHY high (VPH) supply voltage to precede low (VP)
– Added row: RGMII I/O supply voltage
– Added row, V
in
/V
out
input/output voltage range (non-DDR pins) distinguishing between DDR pins.
– Changed maximum value for V
in
/V
out
input/output voltage range DDR pins to OVDD+0.4.
– Added footnotes to both maximum values of V
in
/V
out
input/output voltage range.
– Added row: USB_OTG_CHD_B
• Section 4.1.2, “Thermal Resistance” on page 22: Added NOTE: “Per JEDEC JESD51-2, the intent of
thermal resistance measurements…”.
• Section 4.1.5, “Maximum Measured Supply Currents” on page 26: Clarified language throughout this
section regarding the use case to estimate the maximum supply current.
• Section 4.2.1, “Power-Up Sequence” on page 33:
– Removed content about calculating the proper current limiting resistor for a coin cell.
– Removed inference to internal POR.
• Section 4.5.2, “OSC32K” on page 37: Removed content about calculating the proper current limiting
resistor for a coin cell.
• Section 4.6.1, “XTALI and RTC_XTALI (Clock Inputs) DC Parameters” on page 39:
– Added “NOTE: The Vil and Vih specifications only apply when an external clock source is used…”.
(Revision History table continues on next page.)
Table 99. i.MX 6Dual/6Quad Data Sheet Document Revision History (continued)
Rev.
Number
Date Substantive Change(s)