Datasheet

i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018
132 NXP Semiconductors
Electrical Characteristics
NOTE
• All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
AUDx_TXC/AUDx_RXC and/or the frame sync
AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.
• All timings are on Audiomux Pads when SSI is being used for data
transfer.
• AUDx_TXC and AUDx_RXC refer to the Transmit and Receive
sections of the SSI.
• The terms, WL and BL, refer to Word Length (WL) and Bit Length(BL).
• For internal Frame Sync operation using external clock, the frame sync
timing is same as that of transmit data (for example, during AC97 mode
of operation).
Table 85. SSI Receiver Timing with External Clock
ID Parameter Min Max Unit
External Clock Operation
SS22 AUDx_TXC/AUDx_RXC clock period 81.4 — ns
SS23 AUDx_TXC/AUDx_RXC clock high period 36 — ns
SS24 AUDx_TXC/AUDx_RXC clock rise time — 6.0 ns
SS25 AUDx_TXC/AUDx_RXC clock low period 36 — ns
SS26 AUDx_TXC/AUDx_RXC clock fall time — 6.0 ns
SS28 AUDx_RXC high to AUDx_TXFS (bl) high –10 15.0 ns
SS30 AUDx_RXC high to AUDx_TXFS (bl) low 10 — ns
SS32 AUDx_RXC high to AUDx_TXFS (wl) high –10 15.0 ns
SS34 AUDx_RXC high to AUDx_TXFS (wl) low 10 — ns
SS35 AUDx_TXC/AUDx_RXC External AUDx_TXFS rise time — 6.0 ns
SS36 AUDx_TXC/AUDx_RXC External AUDx_TXFS fall time — 6.0 ns
SS40 AUDx_RXD setup time before AUDx_RXC low 10 — ns
SS41 AUDx_RXD hold time after AUDx_RXC low 2 — ns