Datasheet

i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018
112 NXP Semiconductors
Electrical Characteristics
4.12.12.6 High-Speed Clock Timing
Figure 69. DDR Clock Definition
4.12.12.7 Forward High-Speed Data Transmission Timing
The timing relationship of the DDR Clock differential signal to the Data differential signal is shown in
Figure 70:
Figure 70. Data to Clock Timing Definitions
4.12.12.8 Reverse High-Speed Data Transmission Timing
Figure 71. Reverse High-Speed Data Transmission Timing at Slave Side
L
S
Equivalent wire bond series inductance — — — 1.5 nH
R
S
Equivalent wire bond series resistance — — — 0.15 Ω
R
L
Load Resistance — 80 100 125 Ω
Table 69. Electrical and Timing Information (continued)
Symbol Parameters Test Conditions Min Typ Max Unit
1 Data Bit Time = 1UI
UI
INST
(1)
1 Data Bit Time = 1UI
UI
INST
(2)
CLKp
CLKn
1 DDR Clock Period = UI
INST
(1) + UI
INST
(2)
#,+P
2EFERENCE4IME
4
#,+P
4
3%450
4
(/,$
5)
).34
4
3+%7
5)
).34

#,+N
T
TD
2UI 2UI
CLKp
CLKn
Clock to Data
Skew
NRZ Data