Datasheet

Electrical Characteristics
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018
NXP Semiconductors 111
t
CDC
DDR CLK duty cycle t
CDC
= t
CPH
/ P
DDRCLK
—50—%
t
CPH
DDR CLK high time — — 1 — UI
t
CPL
DDR CLK low time — — 1 — UI
— DDR CLK / DATA Jitter — — 75 — ps pk-pk
t
SKEW[PN]
Intra-Pair (Pulse) skew — — 0.075 — UI
t
SKEW[TX]
Data to Clock Skew — 0.350 — 0.650 UI
t
r
Differential output signal rise time 20% to 80%, RL = 50 Ω 150 — 0.3UI ps
t
f
Differential output signal fall time 20% to 80%, RL = 50 Ω 150 — 0.3UI ps
ΔV
CMTX(HF)
Common level variation above 450 MHz 80 Ω<= RL< = 125 Ω ——15mV
rms
ΔV
CMTX(LF)
Common level variation between 50
MHz and 450 MHz
80 Ω<= RL< = 125 Ω ——25mV
p
LP Line Drivers AC Specifications
t
rlp,
t
flp
Single ended output rise/fall time 15% to 85%, C
L
<70 pF — — 25 ns
t
reo
— 30% to 85%, C
L
<70 pF — — 35 ns
δV/δt
SR
Signal slew rate 15% to 85%, C
L
<70 pF — — 120 mV/ns
C
L
Load capacitance — 0 — 70 pF
HS Line Receiver AC Specifications
t
SETUP[RX]
Data to Clock Receiver Setup time — 0.15 — — UI
t
HOLD[RX]
Clock to Data Receiver Hold time — 0.15 — — UI
ΔV
CMRX(HF)
Common mode interference beyond
450 MHz
— — — 200 mVpp
ΔV
CMRX(LF)
Common mode interference between
50 MHz and 450 MHz
—-50—50mVpp
C
CM
Common mode termination — — — 60 pF
LP Line Receiver AC Specifications
e
SPIKE
Input pulse rejection — — — 300 Vps
T
MIN
Minimum pulse response — 50 — — ns
V
INT
Pk-to-Pk interference voltage — — — 400 mV
f
INT
Interference frequency — 450 — — MHz
Model Parameters used for Driver Load switching performance evaluation
C
PAD
Equivalent Single ended I/O PAD
capacitance.
———1pF
C
PIN
Equivalent Single ended Package +
PCB capacitance.
———2pF
Table 69. Electrical and Timing Information (continued)
Symbol Parameters Test Conditions Min Typ Max Unit