NXP Semiconductors Data Sheet: Technical Data Document Number: IMX6DQAEC Rev. 6, 11/2018 MCIMX6QxAxxxxC MCIMX6QxAxxxxD MCIMX6QxAxxxxE MCIMX6DxAxxxxC MCIMX6DxAxxxxD MCIMX6DxAxxxxE i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors Package Information FCPBGA Package 21 x 21 mm, 0.8 mm pitch Ordering Information See Table 1 1 Introduction The i.MX 6Dual/6Quad automotive and infotainment processors represent the latest achievement in integrated multimedia applications processors.
Introduction • • • Graphics rendering for Human Machine Interfaces (HMI) High-performance speech processing with large databases Audio playback The i.MX 6Dual/6Quad processors offers numerous advanced features, such as: • Multilevel memory system—The multilevel memory system of each processor is based on the L1 instruction and data caches, L2 cache, and internal and external memory.
Introduction 1.1 Ordering Information Table 1 shows examples of orderable part numbers covered by this data sheet. This table does not include all possible orderable part numbers. The latest part numbers are available on nxp.com/imx6series. If your desired part number is not listed in the table, or you have questions about available parts, see nxp.com/imx6series or contact your NXP representative. Table 1.
Introduction Table 1. Example Orderable Part Numbers (continued) 1 Speed1 Grade Temperature Grade Includes GPU, no VPU 1 GHz Automotive 21 mm x 21 mm, 0.8 mm pitch, FCPBGA (lidded) i.MX 6Dual Includes VPU, GPU 852 MHz Automotive 21 mm x 21 mm, 0.8 mm pitch, FCPBGA (lidded) MCIMX6D6AVT08AD i.MX 6Dual Includes VPU, GPU 852 MHz Automotive 21 mm x 21 mm, 0.8 mm pitch, FCPBGA (lidded) MCIMX6D6AVT08AE i.MX 6Dual Includes VPU, GPU 852 MHz Automotive 21 mm x 21 mm, 0.
Introduction MC IMX6 X @ + VV $$ % A Qualification level MC Silicon revision1 A Prototype Samples PC Rev 1.2 C Mass Production MC Rev 1.3 D Special SC Rev 1.6 E Part # series X Fusing % i.MX 6Quad Q Default setting A D HDCP enabled C $$ i.
Introduction • • Frequency of the core (including Neon and L1 cache) as per Table 6.
Introduction • • • – 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR and DDR modes (104 MB/s max) USB: — One High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY — Three USB 2.0 (480 Mbps) hosts: – One HS host with integrated High Speed PHY – Two HS hosts with integrated High Speed Inter-Chip (HS-IC) USB PHY Expansion PCI Express port (PCIe) v2.0 one lane — PCI Express (Gen 2.
Introduction • • • • Support DVFS techniques for low power modes Use Software State Retention and Power Gating for Arm and MPE Support various levels of system power modes Use flexible clock gating control scheme The i.MX 6Dual/6Quad processors use dedicated hardware accelerators to meet the targeted multimedia performance. The use of hardware accelerators is a key factor in obtaining high performance at low power consumption numbers, while having the CPU core relatively free for performing other tasks.
Introduction This standardization applies only to signal names. The ball names are preserved to prevent the need to change schematics, BSDL models, IBIS models, and so on. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev.
Architectural Overview 2 Architectural Overview The following subsections provide an architectural overview of the i.MX 6Dual/6Quad processor system. 2.1 Block Diagram Figure 2 shows the functional modules in the i.MX 6Dual/6Quad processor system.
Modules List 3 Modules List The i.MX 6Dual/6Quad processors contain a variety of digital and analog modules. Table 2 describes these modules in alphabetical order. Table 2. i.MX 6Dual/6Quad Modules List Block Mnemonic Block Name Subsystem Brief Description 512 x 8 Fuse Electrical Fuse Array Security Box Electrical Fuse Array. Enables to setup Boot Modes, Security Levels, Security Keys, and many other system parameters. The i.
Modules List Table 2. i.MX 6Dual/6Quad Modules List (continued) Block Mnemonic Block Name Subsystem Brief Description CSI MIPI CSI-2 Interface Multimedia Peripherals The CSI IP provides MIPI CSI-2 standard camera interface port. The CSI-2 interface supports up to 1 Gbps for up to 3 data lanes and up to 800 Mbps for 4 data lanes. CSU Central Security Unit Security The Central Security Unit (CSU) is responsible for setting comprehensive security policy within the i.MX 6Dual/6Quad platform.
Modules List Table 2. i.MX 6Dual/6Quad Modules List (continued) Block Mnemonic EPIT-1 EPIT-2 ESAI FlexCAN-1 FlexCAN-2 GPIO-1 GPIO-2 GPIO-3 GPIO-4 GPIO-5 GPIO-6 GPIO-7 Block Name Subsystem Brief Description Enhanced Periodic Interrupt Timer Timer Peripherals Each EPIT is a 32-bit “set and forget” timer that starts counting after the EPIT is enabled by software. It is capable of providing precise interrupts at regular intervals with minimal processor intervention.
Modules List Table 2. i.MX 6Dual/6Quad Modules List (continued) Block Mnemonic Block Name Subsystem Brief Description GPU2Dv2 Graphics Processing Multimedia Unit-2D, ver. 2 Peripherals The GPU2Dv2 provides hardware acceleration for 2D graphics algorithms, such as Bit BLT, stretch BLT, and many other 2D functions. GPU3Dv4 Graphics Processing Multimedia Unit-3D, ver.
Modules List Table 2. i.MX 6Dual/6Quad Modules List (continued) Block Mnemonic LDB Block Name Subsystem LVDS Display Bridge Connectivity Peripherals Brief Description LVDS Display Bridge is used to connect the IPU (Image Processing Unit) to External LVDS Display Interface. LDB supports two channels; each channel has following signals: • One clock pair • Four data pairs Each signal pair contains LVDS special differential pad (PadP, PadM).
Modules List Table 2. i.MX 6Dual/6Quad Modules List (continued) Block Mnemonic ROM 96 KB ROMCP Block Name Boot ROM Subsystem Internal Memory Brief Description Supports secure and regular Boot Modes. Includes read protection on 4K region for content protection ROM Controller with Data Path Patch ROM Controller with ROM Patch support SATA Serial ATA The SATA controller and PHY is a complete mixed-signal IP solution designed to implement SATA II, 3.0 Gbps HDD connectivity.
Modules List Table 2. i.MX 6Dual/6Quad Modules List (continued) Block Mnemonic SSI-1 SSI-2 SSI-3 TEMPMON Block Name I2S/SSI/AC97 Interface Subsystem Connectivity Peripherals Brief Description The SSI is a full-duplex synchronous interface, which is used on the processor to provide connectivity with off-chip audio peripherals. The SSI supports a wide variety of protocols (SSI normal, SSI network, I2S, and AC-97), bit depths (up to 24 bits per word), and clock / frame sync options.
Modules List Table 2. i.MX 6Dual/6Quad Modules List (continued) Block Mnemonic uSDHC-1 uSDHC-2 uSDHC-2 uSDHC-4 VDOA VPU WDOG-1 Block Name Subsystem Brief Description SD/MMC and SDXC Connectivity Enhanced Peripherals Multi-Media Card / Secure Digital Host Controller i.MX 6Dual/6Quad specific SoC characteristics: All four MMC/SD/SDIO controller IPs are identical and are based on the uSDHC IP. They are: • Conforms to the SD Host Controller Standard Specification version 3.
Modules List Table 2. i.MX 6Dual/6Quad Modules List (continued) Block Mnemonic WDOG-2 (TZ) EIM XTALOSC 3.1 Block Name Watchdog (TrustZone) Subsystem Timer Peripherals Brief Description The TrustZone Watchdog (TZ WDOG) timer module protects against TrustZone starvation by providing a method of escaping normal mode and forcing a switch to the TZ mode. TZ starvation is a situation where the normal OS prevents switching to the TZ mode.
Electrical Characteristics 4 Electrical Characteristics This section provides the device and module-level electrical characteristics for the i.MX 6Dual/6Quad processors. 4.1 Chip-Level Conditions This section provides the device-level electrical characteristics for the SoC. See Table 3 for a quick reference to the individual tables and sections. Table 3. i.MX 6Dual/6Quad Chip-Level Conditions For these characteristics, … 4.1.
Electrical Characteristics Table 4. Absolute Maximum Ratings Parameter Description Core supply input voltage (LDO enabled) Core supply input voltage (LDO bypass) Core supply output voltage (LDO enabled) VDD_HIGH_IN supply voltage DDR I/O supply voltage GPIO I/O supply voltage HDMI, PCIe, and SATA PHY high (VPH) supply voltage HDMI, PCIe, and SATA PHY low (VP) supply voltage LVDS, MLB, and MIPI I/O supply voltage (2.
Electrical Characteristics 4.1.2 Thermal Resistance NOTE Per JEDEC JESD51-2, the intent of thermal resistance measurements is solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. 4.1.2.1 FCPBGA Package Thermal Resistance Table 5 provides the FCPBGA package thermal resistance data for the lidded package type. Table 5.
Electrical Characteristics 4.1.3 Operating Ranges Table 6 provides the operating ranges of the i.MX 6Dual/6Quad processors. Table 6. Operating Ranges Parameter Description Run mode: LDO enabled Symbol Min Typ Max1 Unit Comment2 VDD_ARM_IN VDD_ARM23_IN3 1.354 — 1.5 V LDO Output Set Point (VDD_ARM_CAP5) of 1.225 V minimum for operation up to 852 MHz or 996 MHz (depending on the device speed grade). 1.2754 — 1.5 V LDO Output Set Point (VDD_ARM_CAP5) of 1.
Electrical Characteristics Table 6. Operating Ranges (continued) Parameter Description GPIO supplies10 HDMI supply voltages PCIe supply voltages SATA Supply voltages Junction temperature 1 2 3 4 5 6 7 8 9 Symbol Min Typ Max1 NVCC_CSI, NVCC_EIM0, NVCC_EIM1, NVCC_EIM2, NVCC_ENET, NVCC_GPIO, NVCC_LCD, NVCC_NANDF, NVCC_SD1, NVCC_SD2, NVCC_SD3, NVCC_JTAG 1.65 1.8, 2.8, 3.3 3.6 NVCC_LVDS_2P511 NVCC_MIPI 2.25 2.5 2.75 V — HDMI_VP 0.99 1.1 1.3 V — HDMI_VPH 2.25 2.5 2.
Electrical Characteristics 10 All digital I/O supplies (NVCC_xxxx) must be powered under normal conditions whether the associated I/O pins are in use or not, and associated I/O pins need to have a pull-up or pull-down resistor applied to limit any floating gate current. 11 This supply also powers the pre-drivers of the DDR I/O pins; therefore, it must always be provided, even when LVDS is not used. 4.1.4 External Clock Sources Each i.
Electrical Characteristics — At power up, an internal ring oscillator is used. After crystal oscillator is stable, the clock circuit switches over to the crystal oscillator automatically. — Higher accuracy than ring oscillator. — If no external crystal is present, then the ring oscillator is used. The decision to choose a clock source should be based on real-time clock use and precision timeout. 4.1.5 Maximum Measured Supply Currents Power consumption is highly dependent on the application.
Electrical Characteristics Table 8. Maximum Supply Currents Maximum Current Power Supply i.MX 6Quad: VDD_ARM_IN + VDD_ARM23_IN i.MX 6Dual: VDD_ARM_IN i.MX 6Dual: or i.MX 6Quad: VDD_SOC_IN Conditions Unit Power Virus CoreMark • Arm frequency = 996 MHz • Arm LDOs set to 1.3V • Tj = 125°C 3920 2500 mA • Arm frequency = 852 MHz • Arm LDOs set to 1.3V • Tj = 125°C 3630 2260 mA • Arm frequency = 996 MHz • Arm LDOs set to 1.
Electrical Characteristics Table 8. Maximum Supply Currents (continued) Maximum Current Power Supply Conditions Unit Power Virus NVCC_LVDS2P5 — CoreMark NVCC_LVDS2P5 is connected to VDD_HIGH_CAP at the board level. VDD_HIGH_CAP is capable of handing the current required by NVCC_LVDS2P5.
Electrical Characteristics Table 9. Stop Mode Current and Power Consumption (continued) Mode Test Conditions STOP_ON STOP_OFF STANDBY Deep Sleep Mode (DSM) SNVS Only 1 • • • • • Arm LDO set to 0.9 V SoC and PU LDOs set to 1.225 V HIGH LDO set to 2.5 V PLLs disabled DDR is in self refresh • • • • • • Arm LDO set to 0.9 V SoC LDO set to 1.225 V PU LDO is power gated HIGH LDO set to 2.
Electrical Characteristics 4.1.7 USB PHY Current Consumption 4.1.7.1 Power Down Mode In power down mode, everything is powered down, including the VBUS valid detectors, typical condition. Table 10 shows the USB interface current consumption in power down mode. Table 10. USB PHY Current Consumption in Power Down Mode Current VDD_USB_CAP (3.0 V) VDD_HIGH_CAP (2.5 V) NVCC_PLL_OUT (1.1 V) 5.1 μA 1.7 μA <0.
Electrical Characteristics Table 11. SATA PHY Current Drain (continued) Mode Test Conditions Supply Typical Current Unit P1: Transmitter idle, Rx powered down, LOS disabled Single Transceiver SATA_VP 0.67 mA SATA_VPH 0.23 SATA_VP 6.9 SATA_VPH 6.2 SATA_VP 0.53 SATA_VPH 0.11 SATA_VP 0.036 SATA_VPH 0.12 SATA_VP 0.13 SATA_VPH 0.012 SATA_VP 0.008 SATA_VPH 0.
Electrical Characteristics Table 12. PCIe PHY Current Drain (continued) Mode Test Conditions Supply Max Current Unit — PCIE_VP (1.1 V) 12 mA PCIE_VPTX (1.1 V) 2.4 PCIE_VPH (2.5 V) 12 PCIE_VP (1.1 V) 1.3 PCIE_VPTX (1.1 V) 0.18 PCIE_VPH (2.5 V) 0.36 P1: Longer Recovery Time Latency, Lower Power State Power Down 4.1.10 — mA HDMI Maximum Power Consumption Table 13 provides HDMI PHY currents for both Active 3D Tx with LFSR15 data pattern and Power-down modes. Table 13.
Electrical Characteristics 4.2 Power Supplies Requirements and Restrictions The system design must comply with power-up sequence, power-down sequence, and steady state guidelines as described in this section to ensure the reliable operation of the device. Any deviation from these sequences may result in the following situations: • Excessive current during power-up phase • Prevention of the device from booting • Irreversible damage to the processor 4.2.
Electrical Characteristics • power consumption. If boundary scan test is used, SATA_VP and SATA_VPH must remain powered. When the PCIE interface is not used, the PCIE_VP, PCIE_VPH, and PCIE_VPTX supplies should be grounded. The input and output supplies for rest of the ports (PCIE_REXT, PCIE_RX_N, PCIE_RX_P, PCIE_TX_N, and PCIE_TX_P) can remain unconnected. It is recommended not to turn the PCIE_VPH supply OFF while the PCIE_VP supply is ON, as it may lead to excessive power consumption.
Electrical Characteristics to 1.2 V with the nominal default setting as 1.1 V. The LDO_1P1 supplies the 24 MHz oscillator, PLLs, and USB PHY. A programmable brown-out detector is included in the regulator that can be used by the system to determine when the load capability of the regulator is being exceeded to take the necessary steps. Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed.
Electrical Characteristics For additional information, see the i.MX 6Dual/6Quad reference manual (IMX6DQRM). 4.4 4.4.1 PLL Electrical Characteristics Audio/Video PLL Electrical Parameters Table 14. Audio/Video PLL Electrical Parameters 4.4.2 Parameter Value Clock output range 650 MHz ~1.3 GHz Reference clock 24 MHz Lock time <11250 reference cycles 528 MHz PLL Table 15. 528 MHz PLL Electrical Parameters 4.4.
Electrical Characteristics 4.4.5 MLB PLL The MediaLB PLL is necessary in the MediaLB 6-Pin implementation to phase align the internal and external clock edges, effectively tuning out the delay of the differential clock receiver and is also responsible for generating the higher speed internal clock, when the internal-to-external clock ratio is not 1:1. Table 18. MLB PLL Electrical Parameters 4.4.6 Parameter Value Lock time <1.5 ms Arm PLL Table 19. Arm PLL Electrical Parameters 4.5 4.5.
Electrical Characteristics CAUTION The internal RTC oscillator does not provide an accurate frequency and is affected by process, voltage, and temperature variations. NXP strongly recommends using an external crystal as the RTC_XTALI reference. If the internal oscillator is used instead, careful consideration must be given to the timing implications on all of the SoC modules dependent on this clock. The OSC32k runs from VDD_SNVS_CAP, which comes from the VDD_HIGH_IN/VDD_SNVS_IN power mux. Table 20.
Electrical Characteristics ovdd pmos (Rpu) 1 or 0 pdat Voh min Vol max pad Predriver nmos (Rpd) ovss Figure 3. Circuit for Parameters Voh and Vol for I/O Cells 4.6.1 XTALI and RTC_XTALI (Clock Inputs) DC Parameters Table 21 shows the DC parameters for the clock inputs. Table 21. XTALI and RTC_XTALI DC Parameters Parameter Symbol Test Conditions XTALI high-level DC input voltage Vih — XTALI low-level DC input voltage Vil — Min Typ Max Unit 0.8 x NVCC_PLL_OUT — NVCC_PLL_ OUT V 0 — 0.
Electrical Characteristics Table 22. GPIO I/O DC Parameters Parameter Symbol Test Conditions Min Max Unit High-level output voltage1 Voh Ioh = -0.1 mA (DSE2 = 001, 010) Ioh = -1 mA (DSE = 011, 100, 101, 110, 111) OVDD – 0.15 — V Low-level output voltage1 Vol Iol = 0.1 mA (DSE2 = 001, 010) Iol = 1mA (DSE = 011, 100, 101, 110, 111) — 0.15 V High-Level DC input voltage1, 3 Vih — 0.7 × OVDD OVDD V Low-Level DC input voltage1, 3 Vil — 0 0.
Electrical Characteristics Table 23. RGMII I/O 2.5V I/O DC Electrical Parameters1 Parameter Symbol Test Conditions Min Max Units OVDD-0.15 — V — 0.15 V High-level output voltage1 VOH Ioh= -0.1 mA (DSE=001,010) Ioh= -1.0 mA (DSE=011,100,101,110,111) Low-level output voltage1 VOL Iol= 0.1 mA (DSE=001,010) Iol= 1.0 mA (DSE=011,100,101,110,111) Input Reference Voltage Vref — 0.49xOVDD 0.51xOVDD V VIH — 0.7xOVDD OVDD V VIL — 0 0.3xOVDD V Input Hysteresis(OVDD=1.
Electrical Characteristics Table 24. LPDDR2 I/O DC Electrical Parameters1 Parameters Symbol Test Conditions Min Max Unit High-level output voltage Voh Ioh = -0.1 mA 0.9 × OVDD — V Low-level output voltage Vol Iol = 0.1 mA — 0.1 × OVDD V Input reference voltage Vref — 0.49 × OVDD 0.51 × OVDD DC input High Voltage Vih(dc) — Vref+0.13V OVDD V DC input Low Voltage Vil(dc) — OVSS Vref-0.13V V Vih(diff) — 0.26 See Note 2 — -0.
Electrical Characteristics Table 25. DDR3/DDR3L I/O DC Electrical Parameters (continued) Parameters Symbol Test Conditions Min Max Unit Termination Voltage Vtt Vtt tracking OVDD/2 0.49 × OVDD 0.51 × OVDD V Input current (no pull-up/down) Iin Vin = 0 or OVDD -2.9 2.9 μA MMpupd — -10 10 % Rres — — 10 Ω Rkeep — 105 175 kΩ Pull-up/pull-down impedance mismatch 240 Ω unit calibration resolution Keeper circuit resistance 1 OVDD – I/O power supply (1.425 V–1.575 V for DDR3 and 1.
Electrical Characteristics Table 27. MLB I/O DC Parameters Parameter Symbol Test Conditions Min Max Unit Output Differential Voltage VOD Rload = 50 Ω between padP and padN 300 500 mV Output High Voltage VOH 1.15 1.75 V Output Low Voltage VOL 0.75 1.35 V Common-mode Output Voltage ((Vpad_P + Vpad_N) / 2)) VOCM 1 1.5 Differential Output Impedance ZO 1.6 — 4.
Electrical Characteristics 4.7.1 General Purpose I/O AC Parameters The I/O AC parameters for GPIO in slow and fast modes are presented in the Table 28 and Table 29, respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bits in the IOMUXC control registers. Table 28. General Purpose I/O AC Parameters 1.
Electrical Characteristics 4.7.2 DDR I/O AC Parameters For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported DDR3/DDR3L/LPDDR2 Configurations.” Table 30 shows the AC parameters for DDR I/O operating in LPDDR2 mode. Table 30. DDR I/O LPDDR2 Mode AC Parameters1 Parameter Symbol Test Condition Min Typ Max Unit Vih(ac) — Vref + 0.22 — OVDD V Vil(ac) — 0 — Vref – 0.22 V AC differential input high voltage Vidh(ac) — 0.
Electrical Characteristics Table 31. DDR I/O DDR3/DDR3L Mode AC Parameters1 (continued) Parameter Single output slew rate, measured between Vol(ac) and Voh(ac) Skew between pad rise/fall asymmetry + skew caused by SSN Symbol Test Condition Min Typ Max Unit tsr Driver impedance = 34 Ω 2.5 — 5 V/ns tSKD clk = 533 MHz — — 0.1 ns 1 Note that the JEDEC JESD79_3C specification supersedes any specification in this document.
Electrical Characteristics padp VOH 0V 0V (Differential) padn VOL 80% 80% 0V 0V VDIFF 20% VDIFF = {padp} - {padn} 20% tTHL tTLH Figure 7. Differential MLB Driver Transition Time Waveform A 4-stage pipeline is used in the MLB 6-pin implementation to facilitate design, maximize throughput, and allow for reasonable PCB trace lengths. Each cycle is one ipp_clk_in* (internal clock from MLB PLL) clock period. Cycles 2, 3, and 4 are MLB PHY related.
Electrical Characteristics 4.8 Output Buffer Impedance Parameters This section defines the I/O impedance parameters of the i.MX 6Dual/6Quad processors for the following I/O types: • General Purpose I/O (GPIO) • Double Data Rate I/O (DDR) for LPDDR2, and DDR3 modes • LVDS I/O • MLB I/O NOTE GPIO and DDR I/O output driver impedance is measured with “long” transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission line.
Electrical Characteristics OVDD PMOS (Rpu) Ztl Ω, L = 20 inches ipp_do pad predriver Cload = 1p NMOS (Rpd) OVSS U,(V) Vin (do) VDD t,(ns) 0 U,(V) Vout (pad) OVDD Vref2 Vref1 Vref t,(ns) 0 Vovdd – Vref1 Rpu = Vref1 Rpd = Vref2 × Ztl × Ztl Vovdd – Vref2 Figure 9. Impedance Matching Load for Measurement i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev.
Electrical Characteristics 4.8.1 GPIO Output Buffer Impedance Table 34 shows the GPIO output buffer impedance (OVDD 1.8 V). Table 34. GPIO Output Buffer Average Impedance (OVDD 1.8 V) Parameter Output Driver Impedance Symbol Drive Strength (DSE) Typ Value Unit Rdrv 001 010 011 100 101 110 111 260 130 90 60 50 40 33 Ω Table 35 shows the GPIO output buffer impedance (OVDD 3.3 V). Table 35. GPIO Output Buffer Average Impedance (OVDD 3.
Electrical Characteristics 4.8.2 DDR I/O Output Buffer Impedance For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported DDR3/DDR3L/LPDDR2 Configurations.” Table 36 shows DDR I/O output buffer impedance of i.MX 6Dual/6Quad processors. Table 36. DDR I/O Output Buffer Impedance Typical Parameter Output Driver Impedance Symbol Test Conditions Rdrv Drive Strength (DSE) = 000 001 010 011 100 101 110 111 NVCC_DRAM=1.5 V (DDR3) DDR_SEL=11 NVCC_DRAM=1.
Electrical Characteristics 4.9 System Modules Timing This section contains the timing and electrical parameters for the modules in each i.MX 6Dual/6Quad processor. 4.9.1 Reset Timing Parameters Figure 10 shows the reset timing and Table 38 lists the timing parameters. SRC_POR_B (Input) CC1 Figure 10. Reset Timing Diagram Table 38. Reset Timing Parameters ID CC1 4.9.
Electrical Characteristics 4.9.3 External Interface Module (EIM) The following subsections provide information on the EIM. Maximum operating frequency for EIM data transfer is 104 MHz. Timing parameters in this section that are given as a function of register settings or clock periods are valid for the entire range of allowed frequencies (0–104 MHz). 4.9.3.1 EIM Interface Pads Allocation EIM supports 32-bit, 16-bit and 8-bit devices operating in address/data separate or multiplexed modes.
Electrical Characteristics 4.9.3.2 General EIM Timing-Synchronous Mode Figure 12, Figure 13, and Table 41 specify the timings related to the EIM module. All EIM output control signals may be asserted and deasserted by an internal clock synchronized to the EIM_BCLK rising edge according to corresponding assertion/negation control fields. WE2 EIM_BCLK ...
Electrical Characteristics Table 41. EIM Bus Timing Parameters (continued) ID 1 2 Parameter Min1 Max1 Unit WE4 Clock rise to address valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns WE5 Clock rise to address invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns WE6 Clock rise to EIM_CSx_B valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns WE7 Clock rise to EIM_CSx_B invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns WE8 Clock rise to EIM_WE_B valid -0.
Electrical Characteristics Figure 14 to Figure 17 provide few examples of basic EIM accesses to external memory devices with the timing parameters mentioned previously for specific control parameters settings. EIM_BCLK EIM_ADDRxx WE5 WE4 Address v1 Last Valid Address WE6 WE6 WE7 EIM_CSx_B EIM_WE_B WE14 WE15 EIM_LBA_B WE10 WE11 WE12 WE13 EIM_OE_B EIM_EBx_B WE18 WE19 D(v1) EIM_DATAxx Figure 14.
Electrical Characteristics EIM_BCLK EIM_ADDRxx/ EIM_ADxx Last Valid Address EIM_CSx_B EIM_WE_B WE17 WE16 WE5 WE4 Write Data Address V1 WE6 WE7 WE8 WE9 WE15 WE14 EIM_LBA_B EIM_OE_B WE10 WE11 EIM_EBx_B Figure 16. Muxed Address/Data (A/D) Mode, Synchronous Write Access, WSC=6,ADVA=0, ADVN=1, and ADH=1 NOTE In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the data bus.
Electrical Characteristics 4.9.3.4 General EIM Timing-Asynchronous Mode Figure 18 through Figure 22 and Table 42 provide timing parameters relative to the chip select (CS) state for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the timing parameters mentioned above. Asynchronous read and write access length in cycles may vary from what is shown in Figure 18 through Figure 21 as RWSC, OEN & CSN is configured differently. See the i.
Electrical Characteristics end of access start of access INT_CLK MAXCSO EIM_CSx_B MAXDI WE31 EIM_ADDRxx/ EIM_ADxx D(V1) Addr. V1 WE44 WE32A EIM_WE_B WE40A WE39 EIM_LBA_B WE35A WE36 EIM_OE_B WE37 EIM_EBx_B WE38 MAXCO Figure 19. Asynchronous A/D Muxed Read Access (RWSC = 5) EIM_CSx_B WE31 EIM_ADDRxx Last Valid Address WE32 Next Address Address V1 WE33 WE34 WE39 WE40 WE45 WE46 EIM_WE_B EIM_LBA_B EIM_OE_B EIM_EBx_B WE42 EIM_DATAxx WE41 D(V1) Figure 20.
Electrical Characteristics EIM_CSx_B WE31 EIM_ADDRxx/ EIM_DATAxx WE41A D(V1) Addr. V1 WE42 WE32A WE33 WE34 EIM_WE_B WE39 EIM_LBA_B WE40A EIM_OE_B WE45 WE46 EIM_EBx_B Figure 21. Asynchronous A/D Muxed Write Access EIM_CSx_B WE31 EIM_ADDRxx Last Valid Address WE32 Next Address Address V1 EIM_WE_B WE39 WE40 WE35 WE36 WE37 WE38 EIM_LBA_B EIM_OE_B EIM_EBx_B WE44 D(V1) EIM_DATAxx[07:00] WE43 WE48 EIM_DTACK_B WE47 Figure 22. DTACK Mode Read Access (DAP=0) i.
Electrical Characteristics EIM_CSx_B WE31 EIM_ADDRxx Last Valid Address WE32 Next Address Address V1 WE33 WE34 WE39 WE40 WE45 WE46 EIM_WE_B EIM_LBA_B EIM_OE_B EIM_EBx_B WE42 EIM_DATAxx WE41 D(V1) WE48 EIM_DTACK_B WE47 Figure 23. DTACK Mode Write Access (DAP=0) Table 42. EIM Asynchronous Timing Parameters Relative to Chip Select1, 2 Ref No. Parameter Determination by Synchronous measured parameters Min Max Unit WE31 EIM_CSx_B valid to Address Valid WE4-WE6-CSA×t -3.5-CSA×t 3.
Electrical Characteristics Table 42. EIM Asynchronous Timing Parameters Relative to Chip Select1, 2 (continued) Ref No. WE40 Parameter EIM_LBA_B Invalid to EIM_CSx_B Invalid (ADVL is asserted) Determination by Synchronous measured parameters Min Max Unit WE7-WE15-CSN×t -3.5-CSN×t 3.5-CSN×t ns 3.5+(ADVN+ADVA +1-CSA)×t ns 3.5-WCSA×t ns WE40A EIM_CSx_B Valid to EIM_LBA_B WE14-WE6+(ADVN+ADVA+1- -3.
Electrical Characteristics 2 In this table: • t means clock period from axi_clk frequency. • CSA means register setting for WCSA when in write operations or RCSA when in read operations. • CSN means register setting for WCSN when in write operations or RCSN when in read operations. • ADVN means register setting for WADVN when in write operations or RADVN when in read operations. • ADVA means register setting for WADVA when in write operations or RADVA when in read operations. 4.
Electrical Characteristics 4.11.1 Asynchronous Mode AC Timing (ONFI 1.0 Compatible) Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The Maximum I/O speed of GPMI in Asynchronous mode is about 50 MB/s. Figure 24 through Figure 27 depict the relative timing between GPMI signals at the module level for different operations under Asynchronous mode. Table 44 describes the timing parameters (NF1–NF17) that are shown in the figures. .!.$?#% ?" NF2 NF1 .!.
Electrical Characteristics .!.$?#,% .!.$?#% ?" NF14 .!.$?2%?" .!.$?2%!$9?" NF15 NF13 NF12 NF16 .!.$?$!4!XX NF17 Data from NF Figure 27. Read Data Latch Cycle Timing Diagram (Non-EDO Mode) .!.$?#,% .!.$?#% ?" NF14 NF13 .!.$?2%?" .!.$?2%!$9?" NF15 NF12 NF17 NF16 NAND_DATAxx Data from NF Figure 28. Read Data Latch Cycle Timing Diagram (EDO Mode) Table 44.
Electrical Characteristics Table 44. Asynchronous Mode Timing Parameters1 (continued) ID 1 2 3 4 5 6 Parameter Timing T = GPMI Clock Cycle Symbol Unit Min Max NF16 Data setup on read tDSR — (DS × T -0.67)/18.38 [see 5,6] ns NF17 Data hold on read tDHR 0.82/11.83 [see 5,6] — ns The GPMI asynchronous mode output timing can be controlled by the module’s internal registers HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.
Electrical Characteristics 4.11.2 Source Synchronous Mode AC Timing (ONFI 2.x Compatible) Figure 29 shows the write and read timing of Source Synchronous mode. .!.$?#%?" NF19 NF18 NF23 NAND_CLE NF25 NF26 NF24 NAND_ALE NF25 NF26 NAND_WE/RE_B NF22 NAND_CLK NAND_DQS NAND_DQS Output enable NF20 NF20 NF21 NF21 NAND_DATA[7:0] CMD ADD NAND_DATA[7:0] Output enable Figure 29. Source Synchronous Mode Command and Address Timing Diagram i.
Electrical Characteristics .!.$?#% ?" NF19 NF18 NF23 .!.$?#,% NF23 .!.$?!,% NF25 NF26 NF25 NF26 NF24 NF24 NAND_WE/RE_B NF22 .!.$?#,+ NF27 NF27 .!.$?$13 .!.$?$13 Output enable NF29 NF29 .!.$?$1; = NF28 NF28 .!.$?$1; = Output enable Figure 30. Source Synchronous Mode Data Write Timing Diagram .!.$?#%?" NF18 NF19 NF23 .!.$?#,% NAND_ALE .!.$?7% 2% NF23 NF25 NF26 NF25 NF26 NF24 NF24 NF25 NF25 NF22 NF26 .!.$?#,+ .!.$?$13 .!.$?$13 /UTPUT ENABLE .!.$?$!4!; = .!.
Electrical Characteristics .!.$?$13 NF30 .!.$?$!4!; = D0 NF30 D1 D2 D3 NF31 NF31 Figure 32. NAND_DQS/NAND_DQ Read Valid Window Table 45. Source Synchronous Mode Timing Parameters1 ID Parameter Symbol Timing T = GPMI Clock Cycle Min NF18 NAND_CEx_B access time NF19 NAND_CEx_B hold time tCE tCH Unit Max CE_DELAY × T - 0.79 [see 2] 0.5 × tCK - 0.63 [see 2] ns ns NF20 Command/address NAND_DATAxx setup time tCAS 0.5 × tCK - 0.05 ns NF21 Command/address NAND_DATAxx hold time tCAH 0.
Electrical Characteristics 4.11.3 4.11.3.1 Samsung Toggle Mode AC Timing Command and Address Timing Samsung Toggle mode command and address timing is the same as ONFI 1.0 compatible Async mode AC timing. See Section 4.11.1, “Asynchronous Mode AC Timing (ONFI 1.0 Compatible)” for details. 4.11.3.2 Read and Write Timing DEV?CLK .!.$?#%X?" .!.$?#,% .!.$?!,% .!.$?7%?" .!.$?2%?" .& .& .!.$?$13 .!.$?$!4!; = T#+ T#+ Figure 33. Samsung Toggle Mode Data Write Timing i.
Electrical Characteristics DEV?CLK .!.$?#%X?" .& .!.$?#,% .!.$?!,% .!.$?7%?" T #+ .& T #+ .& .!.$?2%?" T #+ T #+ T #+ .!.$?$13 .!.$?$!4!; = Figure 34. Samsung Toggle Mode Data Read Timing Table 46.
Electrical Characteristics Table 46. Samsung Toggle Mode Timing Parameters1 (continued) ID 1 2 3 4 5 6 7 Parameter Symbol Timing T = GPMI Clock Cycle Unit Min Max NF28 Data write setup 6 tDS 0.25 × tCK - 0.32 — ns NF29 Data write hold tDH6 0.25 × tCK - 0.79 — ns NF30 NAND_DQS/NAND_DQ read setup skew tDQSQ7 — 3.18 — NF31 NAND_DQS/NAND_DQ read hold skew tQHS7 — 3.
Electrical Characteristics 4.12.2.1 ECSPI Master Mode Timing Figure 35 depicts the timing of ECSPI in master mode and Table 47 lists the ECSPI master mode timing characteristics. ECSPIx_RDY_B CS10 ECSPIx_SS_B CS1 CS2 CS3 CS5 CS6 CS4 ECSPIx_SCLK CS7 CS2 CS3 ECSPIx_MOSI CS8 CS9 ECSPIx_MISO Note: ECSPIx_MOSI is always driven (not tri-stated) between actual data transmissions. This limits the ECSPI to be connected between a single master and a single slave. Figure 35.
Electrical Characteristics 4.12.2.2 ECSPI Slave Mode Timing Figure 36 depicts the timing of ECSPI in slave mode and Table 48 lists the ECSPI slave mode timing characteristics. ECSPIx_SS_B CS2 CS1 CS5 CS6 CS4 ECSPIx_SCLK CS2 CS9 ECSPIx_MISO CS7 CS8 ECSPIx_MOSI Note: ECSPIx_MISO is always driven (not tri-stated) between actual data transmissions. This limits the ECSPI to be connected between a single master and a single slave. Figure 36. ECSPI Slave Mode Timing Diagram Table 48.
Electrical Characteristics 4.12.3 Enhanced Serial Audio Interface (ESAI) Timing Parameters The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. Table 49 shows the interface timing values. The number field in the table refers to timing signals found in Figure 37 and Figure 38. Table 49. Enhanced Serial Audio Interface (ESAI) Timing Parameter1,2 ID Symbol Expression2 Min Max Condition3 Unit tSSICC 4 × Tc 4 × Tc 30.0 30.
Electrical Characteristics Table 49. Enhanced Serial Audio Interface (ESAI) Timing (continued) 1 2 3 4 5 6 ID Parameter1,2 Symbol Expression2 Min Max Condition3 Unit 81 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr) low5 — — — — — — 22.0 12.0 x ck i ck ns 82 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) high — — — — — — 19.0 9.0 x ck i ck ns 83 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) low — — — — — — 20.0 10.
Electrical Characteristics 62 63 64 ESAI_TX_CLK (Input/Output) 78 ESAI_TX_FS (Bit) Out 79 82 ESAI_TX_FS (Word) Out 83 86 86 84 87 First Bit Data Out Last Bit 89 ESAI_TX_FS (Bit) In 91 90 91 ESAI_TX_FS (Word) In Figure 37. ESAI Transmitter Timing i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev.
Electrical Characteristics 62 63 64 ESAI_RX_CLK (Input/Output) 65 ESAI_RX_FS (Bit) Out 66 69 70 ESAI_RX_FS (Word) Out 72 71 First Bit Data In Last Bit 75 73 ESAI_RX_FS (Bit) In 74 75 ESAI_RX_FS (Word) In Figure 38. ESAI Receiver Timing i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev.
Electrical Characteristics Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) 4.12.4 AC Timing This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single Data Rate) timing and eMMC4.4/4.1 (Dual Date Rate) timing. 4.12.4.1 SD/eMMC4.3 (Single Data Rate) AC Timing Figure 39 depicts the timing of SD/eMMC4.3, and Table 50 lists the SD/eMMC4.3 timing characteristics.
Electrical Characteristics Table 50. SD/eMMC4.3 Interface Timing Specification (continued) ID Parameter Symbols Min Max Unit eSDHC Input/Card Outputs SD_CMD, SD_DATAx (Reference to SDx_CLK) SD7 eSDHC Input Setup Time SD8 4 eSDHC Input Hold Time tISU 2.5 — ns tIH 1.5 — ns 1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz.
Electrical Characteristics 4.12.4.3 SDR50/SDR104 AC Timing Figure 41 depicts the timing of SDR50/SDR104, and Table 52 lists the SDR50/SDR104 timing characteristics. SD1 SD2 SD3 SCK SD5 SD4 Output from uSDHC to card SD7 SD6 Input from card to uSDHC SD8 Figure 41. SDR50/SDR104 Timing Table 52. SDR50/SDR104 Interface Timing Specification ID Parameter Symbols Min Max Unit Card Input Clock SD1 Clock Frequency Period tCLK 4.8 — ns SD2 Clock Low Time tCL 0.46 × tCLK 0.
Electrical Characteristics 4.12.4.4 Bus Operation Condition for 3.3 V and 1.8 V Signaling Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50 mode is 1.8 V. The DC parameters for the NVCC_SD1, NVCC_SD2, and NVCC_SD3 supplies are identical to those shown in Table 22, “GPIO I/O DC Parameters,” on page 40. 4.12.5 Ethernet Controller (ENET) AC Electrical Specifications 4.12.5.
Electrical Characteristics 4.12.5.1.2 MII Transmit Signal Timing (ENET_TX_DATA3,2,1,0, ENET_TX_EN, ENET_TX_ER, and ENET_TX_CLK) The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the ENET_TX_CLK frequency. Figure 43 shows MII transmit signal timings. Table 54 describes the timing parameters (M5–M8) shown in the figure.
Electrical Characteristics Table 55. MII Asynchronous Inputs Signal Timing ID M91 1 Characteristic ENET_CRS to ENET_COL minimum pulse width Min Max Unit 1.5 — ENET_TX_CLK period ENET_COL has the same timing in 10-Mbit 7-wire interface mode. 4.12.5.1.4 MII Serial Management Channel Timing (ENET_MDIO and ENET_MDC) The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3 MII specification.
Electrical Characteristics 4.12.5.2 RMII Mode Timing In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference clock. ENET_RX_EN is used as the ENET_RX_EN in RMII. Other signals under RMII mode include ENET_TX_EN, ENET0_TXD[1:0], ENET_RXD[1:0] and ENET_RX_ER. Figure 46 shows RMII mode timings. Table 57 describes the timing parameters (M16–M21) shown in the figure.
Electrical Characteristics 4.12.5.3 RGMII Signal Switching Specifications The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver devices. Table 58. RGMII Signal Switching Specifications1 Symbol Tcyc2 Description Clock cycle duration TskewT3 Data to clock output skew at transmitter TskewR3 Min Max Unit 7.2 8.8 ns -100 900 ps Data to clock input skew at receiver 1 2.
Electrical Characteristics Figure 48. RGMII Receive Signal Timing Diagram Original Figure 49. RGMII Receive Signal Timing Diagram with Internal Delay 4.12.6 Flexible Controller Area Network (FlexCAN) AC Electrical Specifications The Flexible Controller Area Network (FlexCAN) module is a communication controller implementing the CAN protocol according to the CAN 2.0B protocol specification.The processor has two CAN modules available for systems design.
Electrical Characteristics Power-up time for the HDMI 3D Tx PHY while operating with the fastest input reference clock supported (340 MHz) is 133 μs. 4.12.7.2 Electrical Characteristics The table below provides electrical characteristics for the HDMI 3D Tx PHY. The following three figures illustrate various definitions and measurement conditions specified in the table below. Figure 50. Driver Measuring Conditions Figure 51. Driver Definitions Figure 52. Source Termination Table 59.
Electrical Characteristics Table 59. Electrical Characteristics (continued) Symbol RT Parameter Termination resistance Condition Min Typ Max Unit — 45 50 55 Ω TMDS drivers DC specifications VOFF VSWING VH VL RTERM RT = 50 Ω For measurement conditions and Single-ended output swing voltage definitions, see the first two figures above. Compliance point TP1 as defined in the HDMI specification, version 1.3a, section 4.2.4.
Electrical Characteristics PTMDSCLK 50% tCPL tCPH Figure 53. TMDS Clock Signal Definitions Figure 54. Eye Diagram Mask Definition for HDMI Driver Signal Specification at TP1 Figure 55. Intra-Pair Skew Definition i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev.
Electrical Characteristics Figure 56. Inter-Pair Skew Definition Figure 57. TMDS Output Signals Rise and Fall Time Definition Table 60. Switching Characteristics Symbol Parameter Conditions Min Typ Max Unit — — 3.4 Gbps 25 — 340 MHz 2.94 — 40 ns 40 50 60 % TMDS Drivers Specifications — F TMDSCLK P TMDSCLK t CDC t — TMDSCLK frequency On TMDSCLKP/N outputs TMDSCLK period RL = 50 Ω See Figure 53. TMDSCLK duty cycle t CDC =t CPH /P TMDSCLK RL = 50 Ω See Figure 53.
Electrical Characteristics Table 60. Switching Characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit 75 — 0.4 UI ps tF Differential output signal fall time 20–80% RL = 50 Ω See Figure 57. — Differential signal overshoot Referred to 2x VSWING — — 15 % — Differential signal undershoot Referred to 2x VSWING — — 25 % — — 3.
Electrical Characteristics Table 61. I2C Module Timing Parameters (continued) Standard Mode ID IC9 Fast Mode Parameter Bus free time between a STOP and START condition Unit Min Max Min 4.7 — 1.3 Max — µs 4 300 ns IC10 Rise time of both I2Cx_SDA and I2Cx_SCL signals — 1000 20 + 0.1Cb IC11 Fall time of both I2Cx_SDA and I2Cx_SCL signals — 300 20 + 0.
Electrical Characteristics 4.12.10.1 IPU Sensor Interface Signal Mapping The IPU supports a number of sensor input formats. Table 62 defines the mapping of the Sensor Interface Pins used for various supported interface formats. Table 62.
Electrical Characteristics 2 3 4 5 6 7 8 The MSB bits are duplicated on LSB bits implementing color extension. The two MSB bits are duplicated on LSB bits implementing color extension. YCbCr, 8 bits—Supported within the BT.656 protocol (sync embedded within the data stream). RGB, 16 bits—Supported in two ways: (1) As a “generic data” input—with no on-the-fly processing; (2) With on-the-fly processing, but only under some restrictions on the control protocol.
Electrical Characteristics stops receiving data from the stream. For the next line, the IPU2_CSIx_HSYNC timing repeats. For the next frame, the IPU2_CSIx_VSYNC timing repeats. 4.12.10.2.3 Non-Gated Clock Mode The timing is the same as the gated-clock mode (described in Section 4.12.10.2.2, “Gated Clock Mode,”) except for the IPU2_CSIx_HSYNC signal, which is not used (see Figure 60). All incoming pixel clocks are valid and cause data to be latched into the input FIFO.
Electrical Characteristics 4.12.10.3 Electrical Characteristics Figure 61 depicts the sensor interface timing. IPU2_CSIx_PIX_CLK signal described here is not generated by the IPU. Table 63 lists the sensor interface timing characteristics. IPUx_CSIx_PIX_CLK (Sensor Output) IP3 1/IP1 IP2 IPUx_CSIx_DATA_EN, IPUx_CSIx_VSYNC, IPUx_CSIx_HSYNC Figure 61. Sensor Interface Timing Diagram Table 63.
Electrical Characteristics Table 64. Video Signal Cross-Reference (continued) i.
Electrical Characteristics Table 64. Video Signal Cross-Reference (continued) i.
Electrical Characteristics There are special physical outputs to provide synchronous controls: • The ipp_disp_clk is a dedicated base synchronous signal that is used to generate a base display (component, pixel) clock for a display. • The ipp_pin_1– ipp_pin_7 are general purpose synchronous pins, that can be used to provide HSYNC, VSYNC, DRDY or any else independent signal to a display. The IPU has a system of internal binding counters for internal events (such as, HSYNC/VSYNC) calculation.
Electrical Characteristics 4.12.10.6.2 LCD Interface Functional Description Figure 62 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure, signals are shown with negative polarity. The sequence of events for active matrix interface timing is: • DI_CLK internal DI clock is used for calculation of other controls. • IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is selected). In active mode, IPP_DISP_CLK runs continuously.
Electrical Characteristics IP13o IP7 IP5o IP8o IP5 IP8 DI clock IPP_DISP_CLK VSYNC HSYNC DRDY IPP_DATA D0 local start point local start point Dn IP9o IP9 local start point D1 IP10 IP6 Figure 63. TFT Panels Timing Diagram—Horizontal Sync Pulse Figure 64 depicts the vertical timing (timing of one frame). All parameters shown in the figure are programmable. Start of frame End of frame IP13 VSYNC DRDY IP11 HSYNC IP15 IP14 IP12 Figure 64. TFT Panels Timing Diagram—Vertical Sync Pulse i.
Electrical Characteristics Table 65 shows timing characteristics of signals presented in Figure 63 and Figure 64. Table 65.
Electrical Characteristics Table 65. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued) ID Symbol Value Todicp DISP_CLK_OFFSET × Tdiclk IP13o Offset of VSYNC Tovs IP8o Offset of HSYNC IP9o Offset of DRDY IP5o 1 Parameter Offset of IPP_DISP_CLK Description Unit DISP_CLK_OFFSET—offset of IPP_DISP_CLK edges from local start point, in DI_CLK×2 (0.5 DI_CLK Resolution). Defined by DISP_CLK counter.
Electrical Characteristics Figure 65 depicts the synchronous display interface timing for access level. The DISP_CLK_DOWN and DISP_CLK_UP parameters are register-controlled. Table 66 lists the synchronous display interface timing characteristics. IP20o IP20 VSYNC HSYNC DRDY other controls IPP_DISP_CLK Tdicu Tdicd IPP_DATA IP16 IP17 IP19 IP18 local start point Figure 65. Synchronous Display Interface Timing Diagram—Access Level Table 66.
Electrical Characteristics 4.12.11 LVDS Display Bridge (LDB) Module Parameters The LVDS interface complies with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD 644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits.” Table 67.
Electrical Characteristics Table 68. Electrical and Timing Information (continued) Symbol Parameters Test Conditions Min Typ Max Unit HS Line Drivers DC Specifications |VOD| HS Transmit Differential output voltage magnitude 80 Ω<= RL< = 125 Ω 140 200 270 mV Δ|VOD| Change in Differential output voltage magnitude between logic states 80 Ω<= RL< = 125 Ω — — 10 mV VCMTX Steady-state common-mode output voltage.
Electrical Characteristics Table 68. Electrical and Timing Information (continued) Symbol Parameters Test Conditions Min Typ Max Unit LP Line Receiver DC Specifications VIL Input low voltage — — — 550 mV VIH Input high voltage — 920 — — mV VHYST Input hysteresis — 25 — — mV 200 — 450 mV Contention Line Receiver DC Specifications VILF Input low fault threshold — 4.12.12.
Electrical Characteristics 4.12.12.3 HS Line Driver Characteristics Ideal Single-Ended High Speed Signals VDN VCMTX = (VDP + VDN)/2 VOD(0) VOD(1) VDP Ideal Differential High Speed Signals VOD(1) 0V (Differential) VOD(0) VOD = VDP - VDN Figure 67. Ideal Single-ended and Resulting Differential HS Signals 4.12.12.
Electrical Characteristics Table 69. Electrical and Timing Information (continued) Symbol Parameters Test Conditions tCDC = tCPH / PDDRCLK Min Typ Max Unit — 50 — % tCDC DDR CLK duty cycle tCPH DDR CLK high time — — 1 — UI tCPL DDR CLK low time — — 1 — UI — DDR CLK / DATA Jitter — — 75 — ps pk-pk tSKEW[PN] Intra-Pair (Pulse) skew — — 0.075 — UI tSKEW[TX] Data to Clock Skew — 0.350 — 0.
Electrical Characteristics Table 69. Electrical and Timing Information (continued) Symbol Parameters Test Conditions Min Typ Max Unit LS Equivalent wire bond series inductance — — — 1.5 nH RS Equivalent wire bond series resistance — — — 0.15 Ω RL Load Resistance — 80 100 125 Ω 4.12.12.6 High-Speed Clock Timing CLKp CLKn 1 Data Bit Time = 1UI 1 Data Bit Time = 1UI UIINST(1) UIINST(2) 1 DDR Clock Period = UIINST(1) + UIINST(2) Figure 69. DDR Clock Definition 4.12.12.
Electrical Characteristics 4.12.12.9 Low-Power Receiver Timing 2*TLPX eSPIKE 2*TLPX Input TMIN-RX eSPIKE TMIN-RX VIH VIL Output Figure 72. Input Glitch Rejection of Low-Power Receivers 4.12.13 HSI Host Controller Timing Parameters This section describes the timing parameters of the HSI Host Controller which are compliant with High-Speed Synchronous Serial Interface (HSI) Physical Layer specification version 1.01. 4.12.13.
Electrical Characteristics 4.12.13.3 Receiver Real-Time Data Flow First bit of frame t Last bit of frame First bit of frame Last bit of frame NomBit DATA FLAG N-bits Frame N-bits Frame READY Receiver has detected the start of the Frame Receiver has captured a complete Frame Figure 75. Receiver Real-Time Data Flow READY Signal Timing 4.12.13.4 Synchronized Data Flow Transmission with Wake TX state A B C PHY Frame A D PHY Frame DATA FLAG 3. First bit received READY WAKE RX state 1.
Electrical Characteristics 4.12.13.6 Frame Transmission Mode (Synchronized Data Flow) Frame start bit Channel Description bits Payload Data Bits DATA FLAG Complete N-bits Frame Complete N-bits Frame READY Figure 78. Frame Transmission Mode Transfer of Two Frames (Synchronized Data Flow) 4.12.13.7 Frame Transmission Mode (Pipelined Data Flow) Frame start bit Channel Description bits Payload Data Bits DATA FLAG Complete N-bits Frame Complete N-bits Frame READY Figure 79.
Electrical Characteristics 4.12.13.9 DATA and FLAG Signal Timing t 50% DATA (TX) 80% 50% t Note1 50% FLAG (TX) t 50% Note2 Rise 80% 80% 20% t Bit t DATA (RX) EdgeSepTx 20% 20% Fall t TxToRxSkew EdgeSepRx 80% 50% Note2 Note1 50% FLAG (RX) 20% Figure 80. DATA and FLAG Signal Timing 4.12.14 MediaLB (MLB) Characteristics 4.12.14.1 MediaLB (MLB) DC Characteristics Table 71 lists the MediaLB 3-pin interface electrical characteristics. Table 71.
Electrical Characteristics Table 72. MediaLB 6-Pin Interface Electrical DC Specifications (continued) Parameter Symbol Test Conditions Min Max Unit Common-mode output voltage: (VO+ - VO-) / 2 VOCM — 1.0 1.5 V Difference in common-mode output between (high/low) steady-states: I VOCM, high - VOCM, low I ΔVOCM — -50 50 mV Variations on common-mode output during a logic state transitions VCMV See Note2 — 150 mVpp Short circuit current |IOS| See Note3 — 43 mA ZO — 1.
Electrical Characteristics 4.12.14.2 MediaLB (MLB) Controller AC Timing Electrical Specifications This section describes the timing electrical information of the MediaLB module. Figure 81 show the timing of MediaLB 3-pin interface, and Table 73 and Table 74 lists the MediaLB 3-pin interface timing characteristics. Figure 81. MediaLB 3-Pin Timing Ground = 0.
Electrical Characteristics Table 73. MLB 256/512 Fs Timing Parameters (continued) Parameter Bus Hold from MLB_CLK low Transmitter MLBSIG (MLBDAT) output valid from transition of MLBCLK (low-to-high) Symbol Min Max Unit Comment tmdzh 4 — ns — Tdelay — 10.75 — ns 1 The controller can shut off MLB_CLK to place MediaLB in a low-power state. Depending on the time the clock is shut off, a runt pulse can occur on MLB_CLK. 2 MLB_CLK low/high time includes the pulse width variation.
Electrical Characteristics Table 75. MLB 6-Pin Interface Timing Parameters Parameter Symbol Min Max Unit Comment Cycle-to-cycle system jitter tjitter — 600 ps — Transmitter MLB_SIG_P/_N (MLB_DATA_P/_N) output valid from transition of MLB_CLK_P/_N (low-to-high)1 tdelay 0.6 1.3 ns — Disable turnaround time from transition of MLB_CLK_P/_N (low-to-high) tphz 0.6 3.5 ns — Enable turnaround time from transition of MLB_CLK_P/_N (low-to-high) tplz 0.6 5.
Electrical Characteristics 4.12.15.1 PCIE_REXT Reference Resistor Connection The impedance calibration process requires connection of reference resistor 200 Ω. 1% precision resistor on PCIE_REXT pads to ground. It is used for termination impedance calibration. 4.12.16 Pulse Width Modulator (PWM) Timing Parameters This section describes the electrical information of the PWM. The PWM can be programmed to select one of three clock signals as its source frequency.
Electrical Characteristics 4.12.17.1.1 SATA PHY Transmitter Characteristics Table 77 provides specifications for SATA PHY transmitter characteristics. Table 77. SATA PHY Transmitter Characteristics Parameters Transmit common mode voltage Symbol Min Typ Max Unit VCTM 0.4 — 0.6 V — –0.5 — 0.5 dB Transmitter pre-emphasis accuracy (measured change in de-emphasized bit) 4.12.17.1.2 SATA PHY Receiver Characteristics Table 78 provides specifications for SATA PHY receiver characteristics.
Electrical Characteristics JTAG_TCK (Input) VIH VIL SJ5 SJ4 Data Inputs Input Data Valid SJ6 Data Outputs Output Data Valid SJ7 Data Outputs SJ6 Data Outputs Output Data Valid Figure 85. Boundary Scan (JTAG) Timing Diagram JTAG_TCK (Input) VIH VIL SJ8 JTAG_TDI JTAG_TMS (Input) SJ9 Input Data Valid SJ10 JTAG_TDO (Output) Output Data Valid SJ11 JTAG_TDO (Output) SJ10 JTAG_TDO (Output) Output Data Valid Figure 86. Test Access Port Timing Diagram i.
Electrical Characteristics JTAG_TCK (Input) SJ13 JTAG_TRST_B (Input) SJ12 Figure 87. JTAG_TRST_B Timing Diagram Table 79. JTAG Timing All Frequencies Parameter1,2 ID 1 2 Unit Min Max 0.001 22 MHz 45 — ns 22.
Electrical Characteristics Table 80. SPDIF Timing Parameters Timing Parameter Range Parameter Symbol Unit Min Max SPDIF_IN Skew: asynchronous inputs, no specs apply — — 0.7 ns SPDIF_OUT output (Load = 50pf) • Skew • Transition rising • Transition falling — — — — — — 1.5 24.2 31.3 ns SPDIF_OUT output (Load = 30pf) • Skew • Transition rising • Transition falling — — — — — — 1.5 13.6 18.0 ns Modulating Rx clock (SPDIF_SR_CLK) period srckp 40.0 — ns SPDIF_SR_CLK high period srckph 16.
Electrical Characteristics 4.12.20 SSI Timing Parameters This section describes the timing parameters of the SSI module. The connectivity of the serial synchronous interfaces are summarized in Table 81. Table 81.
Electrical Characteristics Table 82. SSI Transmitter Timing with Internal Clock ID Parameter Min Max Unit Internal Clock Operation SS1 AUDx_TXC/AUDx_RXC clock period 81.4 — ns SS2 AUDx_TXC/AUDx_RXC clock high period 36.0 — ns SS4 AUDx_TXC/AUDx_RXC clock low period 36.0 — ns SS6 AUDx_TXC high to AUDx_TXFS (bl) high — 15.0 ns SS8 AUDx_TXC high to AUDx_TXFS (bl) low — 15.0 ns SS10 AUDx_TXC high to AUDx_TXFS (wl) high — 15.
Electrical Characteristics 4.12.20.2 SSI Receiver Timing with Internal Clock Figure 91 depicts the SSI receiver internal clock timing and Table 83 lists the timing parameters for the receiver timing with the internal clock. SS1 SS3 SS5 SS2 SS4 AUDx_TXC (Output) SS9 SS7 AUDx_TXFS (bl) (Output) SS11 SS13 AUDx_TXFS (wl) (Output) SS20 SS21 AUDx_RXD (Input) SS47 SS48 SS51 SS49 SS50 AUDx_RXC (Output) Figure 91. SSI Receiver Internal Clock Timing Diagram Table 83.
Electrical Characteristics Table 83. SSI Receiver Timing with Internal Clock (continued) ID Parameter Min Max Unit 15.04 — ns Oversampling Clock Operation SS47 Oversampling clock period SS48 Oversampling clock high period 6.0 — ns SS49 Oversampling clock rise time — 3.0 ns SS50 Oversampling clock low period 6.0 — ns SS51 Oversampling clock fall time — 3.
Electrical Characteristics 4.12.20.3 SSI Transmitter Timing with External Clock Figure 92 depicts the SSI transmitter external clock timing and Table 84 lists the timing parameters for the transmitter timing with the external clock. SS22 SS25 SS23 SS26 SS24 AUDx_TXC (Input) SS27 SS29 AUDx_TXFS (bl) (Input) SS33 SS31 AUDx_TXFS (wl) (Input) SS39 SS37 SS38 AUDx_TXD (Output) SS45 SS44 AUDx_RXD (Input) Note: AUDx_RXD Input in Synchronous mode only SS46 Figure 92.
Electrical Characteristics Table 84. SSI Transmitter Timing with External Clock (continued) ID Parameter Min Max Unit Synchronous External Clock Operation SS44 AUDx_RXD setup before AUDx_TXC falling 10.0 — ns SS45 AUDx_RXD hold after AUDx_TXC falling 2.0 — ns SS46 AUDx_RXD rise/fall time — 6.0 ns NOTE All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0).
Electrical Characteristics Table 85. SSI Receiver Timing with External Clock ID Parameter Min Max Unit 81.4 — ns External Clock Operation SS22 AUDx_TXC/AUDx_RXC clock period SS23 AUDx_TXC/AUDx_RXC clock high period 36 — ns SS24 AUDx_TXC/AUDx_RXC clock rise time — 6.0 ns SS25 AUDx_TXC/AUDx_RXC clock low period 36 — ns SS26 AUDx_TXC/AUDx_RXC clock fall time — 6.0 ns SS28 AUDx_RXC high to AUDx_TXFS (bl) high –10 15.
Electrical Characteristics 4.12.21 UART I/O Configuration and Timing Parameters 4.12.21.1 UART RS-232 I/O Configuration in Different Modes The i.MX 6Dual/6Quad UART interfaces can serve both as DTE or DCE device. This can be configured by the DCEDTE control bit (default 0 – DCE mode). Table 86 shows the UART I/O configuration based on the enabled mode. Table 86. UART I/O Configuration vs.
Electrical Characteristics 4.12.21.2 UART RS-232 Serial Mode Timing The following sections describe the electrical information of the UART module in the RS-232 mode. 4.12.21.2.1 UART Transmitter Figure 94 depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1 stop bit format. Table 87 lists the UART RS-232 serial mode transmit timing characteristics.
Electrical Characteristics 4.12.21.2.3 UART IrDA Mode Timing The following subsections give the UART transmit and receive timings in IrDA mode. UART IrDA Mode Transmitter Figure 96 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 89 lists the transmit timing characteristics. UA3 UA3 UA4 UA3 UA3 UARTx_TX_DATA (output) Start Bit Bit 0 Bit 1 Bit 3 Bit 2 Bit 4 Bit 5 Bit 6 Bit 7 POSSIBLE PARITY BIT STOP BIT Figure 96.
Electrical Characteristics 4.12.22 USB HSIC Timings This section describes the electrical information of the USB HSIC port. NOTE HSIC is a DDR signal. The following timing specification is for both rising and falling edges. 4.12.22.1 Transmit Timing Tstrobe USB_H_STROBE Todelay Todelay USB_H_DATA Figure 98. USB HSIC Transmit Waveform Table 91. USB HSIC Transmit Parameters Name Parameter Min Max Unit Comment 4.166 4.
Electrical Characteristics 4.12.23 USB PHY Parameters This section describes the USB-OTG PHY and the USB Host port PHY parameters. The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision 2.0 OTG, USB Host with the amendments below (On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification is not applicable to Host port).
Boot Mode Configuration 5 Boot Mode Configuration This section provides information on boot mode configuration pins allocation and boot devices interfaces allocation. 5.1 Boot Mode Configuration Pins Table 93 provides boot options, functionality, fuse values, and associated pins. Several input pins are also sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.
Boot Mode Configuration Table 93.
Boot Mode Configuration Table 94.
Package Information and Contact Assignments 6 Package Information and Contact Assignments This section includes the contact assignment information and mechanical package drawing. 6.1 Signal Naming Convention The signal names of the i.MX6 series of products are standardized to align the signal names within the family and across the documentation.
Package Information and Contact Assignments 6.2.1.1 21 x 21 mm Lidded Package Figure 100 and Figure 101 show the top, bottom, and side views of the 21 × 21 mm lidded package. Figure 100. 21 x 21 mm Lidded Package Top, Bottom, and Side Views (Sheet 1 of 2) i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev.
Package Information and Contact Assignments Figure 101. 21 x 21 mm Lidded Package Top, Bottom, and Side Views (Sheet 2 of 2) i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev.
Package Information and Contact Assignments 6.2.2 21 x 21 mm Ground, Power, Sense, and Reference Contact Assignments Table 95 shows the device connection list for ground, power, sense, and reference contact signals. Table 95.
Package Information and Contact Assignments Table 95.
Package Information and Contact Assignments Table 95. 21 x 21 mm Supplies Contact Assignment (continued) Supply Rail Name Ball(s) Position(s) Remark VDDHIGH_CAP H10, J10 Secondary supply for the 2.5 V domain (internal regulator output—requires capacitor if internal regulator is used) VDDHIGH_IN H9, J9 Primary supply for the 2.
Package Information and Contact Assignments Table 96.
Package Information and Contact Assignments Table 96.
Package Information and Contact Assignments Table 96.
Package Information and Contact Assignments Table 96.
Package Information and Contact Assignments Table 96.
Package Information and Contact Assignments Table 96.
Package Information and Contact Assignments Table 96.
Package Information and Contact Assignments Table 96.
Package Information and Contact Assignments Table 96.
Package Information and Contact Assignments Table 96.
Package Information and Contact Assignments Table 96.
Package Information and Contact Assignments 2 Variance of the pull-up and pull-down strengths are shown in the tables as follows: • Table 22, “GPIO I/O DC Parameters,” on page 40. • Table 24, “LPDDR2 I/O DC Electrical Parameters,” on page 42. • Table 25, “DDR3/DDR3L I/O DC Electrical Parameters,” on page 42. 3 ENET_REF_CLK is used as a clock source for MII and RGMII modes only. RMII mode uses either GPIO_16 or RGMII_TX_CTL as a clock source.
Package Information and Contact Assignments Table 97.
BOOT_MODE1 SD3_DAT7 SD3_DAT1 NANDF_CS0 NANDF_D2 SD4_DAT2 SD1_DAT3 SD2_CMD RGMII_TD1 EIM_D17 SATA_VPH SATA_VP NVCC_SD3 NVCC_NANDF NVCC_SD1 NVCC_SD2 NVCC_RGMII GND EIM_D20 EIM_D19 EIM_A24 PMIC_STBY_REQ VDD_SNVS_IN EIM_A19 USB_H1_DN GND EIM_A22 VDDUSB_CAP VDD_SNVS_CAP EIM_A17 GND PCIE_VPTX EIM_EB3 GND PCIE_VPH EIM_D28 GND JTAG_TDO EIM_D24 GND JTAG_TDI EIM_D25 CSI_CLK0M DSI_REXT CSI_D3M DSI_D0M CSI_CLK0P CSI_D3P DSI_D0P EIM_D27 EIM_D26 EIM_D22 EIM_EB2 RGMII_TD2 SD
NXP Semiconductors CSI0_DAT9 CSI0_DAT8 NVCC_CSI GND VDDARM23_IN GND GPIO_19 GPIO_18 NVCC_GPIO GND VDDARM23_IN GND GND VDDARM23_IN GND HDMI_VPH CSI0_DAT18 CSI0_DAT15 CSI0_DAT14 CSI0_DAT11 CSI0_DAT12 CSI0_DAT10 M GND VDDARM23_IN GND HDMI_VP CSI0_DAT19 GND CSI0_DAT16 CSI0_DAT17 GND CSI0_DAT13 L GND VDDARM23_IN GND NVCC_MIPI HDMI_D0P HDMI_D0M HDMI_D2P HDMI_D2M HDMI_DDCCEC HDMI_HPD K VDDHIGH_CAP VDDHIGH_IN GND NVCC_JTAG HDMI_CLKP HDMI_CLKM HDMI_D1P HDMI_D1M GND HD
DRAM_D10 GND DRAM_D17 DRAM_D23 GND DRAM_D14 DRAM_D16 DRAM_DQM2 DRAM_D18 DRAM_SDQS3_B DRAM_D45 DRAM_D57 DRAM_D41 DRAM_D42 DRAM_SDQS7 GND DRAM_D38 DRAM_D56 DRAM_D33 DRAM_DQM4 DRAM_SDQS7_B DRAM_D32 DRAM_SDODT1 GND GND DRAM_SDWE DRAM_D61 DRAM_A10 DRAM_RAS DRAM_D60 DRAM_A2 DRAM_A1 GND GND DRAM_A8 DRAM_D52 DRAM_A14 DRAM_SDBA2 W LVDS0_TX2_P V DRAM_D25 DRAM_D19 DRAM_D21 DRAM_D20 DRAM_RESET GND LVDS1_CLK_P LVDS1_CLK_N DRAM_D58 GND DRAM_D62 DRAM_D59 DRAM_DQM7 DRAM_D
NXP Semiconductors DRAM_D8 DRAM_SDQS1 GND DRAM_SDQS2 DRAM_D29 GND DRAM_D30 DRAM_A12 GND DRAM_D9 DRAM_SDQS1_B DRAM_D11 DRAM_SDQS2_B DRAM_D24 DRAM_DQM3 DRAM_D26 DRAM_A9 DRAM_A5 9 8 7 6 5 4 3 2 1 DRAM_A0 DRAM_A6 DRAM_A11 DRAM_D31 14 13 12 11 DRAM_SDQS3 10 DRAM_D28 DRAM_D22 DRAM_D15 DRAM_DQM1 DRAM_D13 DRAM_D2 DRAM_DQM0 DRAM_VREF DRAM_D4 AC GND DRAM_CS1 DRAM_SDQS4 GND DRAM_SDQS5 DRAM_D43 GND DRAM_SDQS6 DRAM_DQM6 DRAM_D54 DRAM_CAS ZQPAD DRAM_SDQS4_B DRAM_D35 DRAM_SDQS5_B DRAM_D46 DR
Revision History 7 Revision History Table 99 provides a revision history for the i.MX 6Dual/6Quad data sheet. Table 99. i.MX 6Dual/6Quad Data Sheet Document Revision History Rev. Number 6 Date Substantive Change(s) 10/2018 Revision 6 changes: • Table 21, “XTALI and RTC_XTALI DC Parameters,” on page 39, – Row: XTALI input leakage current at startup, IXTALI_STARTUP: Changed from “... driven 32 KHz RTC clock @ 1.1V” to “...driven 24 MHz clock at 1.1V.” • Table 51, “eMMC4.4/4.
Revision History Table 99. i.MX 6Dual/6Quad Data Sheet Document Revision History (continued) Rev. Number 5 Date Substantive Change(s) 09/2017 Rev. 5 changes include the following: • Changed throughout: – Changed terminology from “floating” to “not connected”. – Removed VADC feature from 19mm x 19mm package. Contact NXP sales and marketing with enablement options. • Section 1, “Introduction” on page 1: Corrected typo in last sentence of first paragraph “aut1omotive”. • Section 1.
Revision History Table 99. i.MX 6Dual/6Quad Data Sheet Document Revision History (continued) Rev. Number 5 (Cont.) Date Substantive Change(s) 09/2017 • Table 21, “XTALI and RTC_XTALI DC Parameters,” on page 39: – Added footnote to RTC_XTALI high level DC input voltage row: “This voltage specification must not be exceeded and …”. Section 4.6.4, “RGMII I/O 2.5V I/O DC Electrical Parameters” on page 40: Added section and table. • Section 4.
Revision History Table 99. i.MX 6Dual/6Quad Data Sheet Document Revision History (continued) Rev. Number 4 Date Substantive Change(s) 07/2015 • Added footnote to Table 1, “Example Orderable Part Numbers,” on page 3: If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz. • Section 1.2, “Features” changed Five UARTs, from up to 4.0 Mbps, to up to 5.0 Mbps.
Revision History Table 99. i.MX 6Dual/6Quad Data Sheet Document Revision History (continued) Rev. Number Rev. 3 Rev. 2.3 Date Substantive Change(s) 02/2014 • Updates throughout for Silicon revision D, include: - Figure 1 Part number nomenclature diagram. - Example Orderable Part Number tables, Table 1 • Feature description for Miscellaneous IPs and interfaces; SSI and ESAI. • Table 6, UART 1–5 description change: programmable baud rate up to 5 MHz.
Revision History Table 99. i.MX 6Dual/6Quad Data Sheet Document Revision History (continued) Rev. Number Rev. 2 Date Substantive Change(s) 04/2013 Substantive changes throughout this document are as follows: • Incorporated standardized signal names. This change is extensive throughout. Added reference to EB792, i.MX Signal Name Mapping. • Figures updated to align to standardized signal names. • Aligned references to FCBGA to read FCPBGA throughout document.
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