INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4046B MSI Phase-locked loop Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors Product specification HEF4046B MSI Phase-locked loop DESCRIPTION The HEF4046B is a phase-locked loop circuit that consists of a linear voltage controlled oscillator (VCO) and two different phase comparators with a common signal input amplifier and a common comparator input. A 7 V regulator (zener) diode is provided for supply voltage regulation if necessary. For functional description see further on in this data. Fig.1 Functional diagram.
Philips Semiconductors Product specification HEF4046B MSI Phase-locked loop PINNING 1. Phase comparator pulse output 2. Phase comparator 1 output 3. Comparator input 4. VCO output 5. Inhibit input 6. Capacitor C1 connection A 7. Capacitor C1 connection B 8. VSS 9. VCO input 10. Source-follower output 11. Resistor R1 connection 12. Resistor R2 connection 13. Phase comparator 2 output 14. Signal input 15. Zener diode input for regulated supply. Fig.2 Pinning diagram.
Philips Semiconductors Product specification HEF4046B MSI Phase-locked loop (1) Average output voltage. Fig.3 Signal-to-comparator inputs phase difference for comparator 1. Figure 4 shows the typical waveforms for a PLL employing phase comparator 1 in locked condition of fo. Fig.4 Typical waveforms for phase-locked loop employing phase comparator 1 in locked condition of fo.
Philips Semiconductors Product specification HEF4046B MSI Phase-locked loop comparator inputs are equal in both phase and frequency. At this stable point, both p and n-type drivers remain OFF and thus the phase comparator output becomes an open circuit and keeps the voltage at the capacitor of the low-pass filter constant. Phase comparator 2 is an edge-controlled digital memory network.
Philips Semiconductors Product specification HEF4046B MSI Phase-locked loop Figure 6 shows the state diagram for phase comparator 2. Each circle represents a state of the comparator. The number at the top, inside each circle, represents the state of the comparator, while the logic state of the signal and comparator inputs are represented by a ‘0’ for a logic LOW or a ‘1’ for a logic HIGH, and they are shown in the left and right bottom of each circle.
Philips Semiconductors Product specification HEF4046B MSI Phase-locked loop DC CHARACTERISTICS VSS = 0 V Tamb (°C) VDD V Supply current −40 SYMBOL 5 + 25 + 85 TYP. MAX. TYP. MAX. − − 20 − TYP. − MAX. − µA − − 300 − − − µA 15 − − 750 − − − µA Quiescent device 5 − 20 − 20 − 150 µA current (note 2) 10 (note 1) 10 ID IDD 15 − 40 − 40 − 300 µA − 80 − 80 − 600 µA Notes 1. Pin 15 open; pin 5 at VDD; pins 3 and 9 at VSS; pin 14 open. 2.
Philips Semiconductors Product specification HEF4046B MSI Phase-locked loop VDD V SYMBOL MIN. TYP. MAX.
Philips Semiconductors Product specification HEF4046B MSI Phase-locked loop DESIGN INFORMATION CHARACTERISTIC USING PHASE COMPARATOR 1 USING PHASE COMPARATOR 2 No signal on SIGNIN VCO in PLL system adjusts to centre frequency (fo) VCO in PLL system adjusts to min.
Philips Semiconductors Product specification HEF4046B MSI Phase-locked loop Fig.7 Typical centre frequency as a function of capacitor C1; Tamb = 25 °C; VCOIN at 1⁄2 VDD; INH at VSS; R2 = ∞.
Philips Semiconductors Product specification HEF4046B MSI Phase-locked loop Fig.8 Typical frequency offset as a function of capacitor C1; Tamb = 25 °C; VCOIN at VSS; INH at VSS; R1 = ∞.
Philips Semiconductors Product specification HEF4046B MSI Phase-locked loop Fig.9 Typical ratio of R2/R1 as a function of the ratio fmax/fmin.
Philips Semiconductors Product specification HEF4046B MSI Phase-locked loop Fig.10 Power dissipation as a function of R1; R2 = ∞; VCOIN at 1⁄2 VDD; CL = 50 pF. Fig.11 Power dissipation as a function of R2; R1 = ∞; VCOIN at VSS (0 V); CL = 50 pF.
Philips Semiconductors Product specification HEF4046B MSI Phase-locked loop Fig.12 Power dissipation of source follower as a function of RSF; VCOIN at 1⁄2 VDD; R1 = ∞ ; R2 = ∞ . For VCO linearity: f1 + f2 ′ f o = -------------2 ′ f o – fo - × 100% lin. = --------------′ fo Figure 13 and the above formula also apply to source follower linearity: substitute VSF OUT for f. ∆V = 0,3 V at VDD = 5 V ∆V = 2,5 V at VDD = 10 V ∆V = 5 V at VDD = 15 V Fig.13 Definition of linearity (see AC characteristics).
Philips Semiconductors Product specification HEF4046B MSI Phase-locked loop Fig.14 VCO frequency linearity as a function of R1; R2 = ∞; VDD = 5 V. Fig.15 VCO frequency linearity as a function of R1; R2 = ∞; VDD = 10 V. Fig.16 VCO frequency linearity as a function of R1; R2 = ∞; VDD = 15 V.
