Datasheet

January 1995 4
Philips Semiconductors Product specification
12-stage binary counter
HEF4040B
MSI
Note
1. For other loads than 50 pF at the n
th
output, use the slope given.
Minimum clock 5 50 25 ns
see also waveforms
Fig.4
pulse width; HIGH 10 t
WCPH
30 15 ns
15 20 10 ns
Minimum MR 5 40 20 ns
pulse width; HIGH 10 t
WMRH
30 15 ns
15 20 10 ns
Recovery time 5 40 20 ns
for MR 10 t
RMR
30 15 ns
15 20 10 ns
Maximum clock 5 10 20 MHz
pulse frequency 10 f
max
15 30 MHz
15 25 50 MHz
V
DD
V
TYPICAL FORMULA FOR P (µW)
Dynamic power 5 400 f
i
+∑(f
o
C
L
) × V
DD
2
where
dissipation per 10 2 000 f
i
+∑(f
o
C
L
) × V
DD
2
f
i
= input freq. (MHz)
package (P) 15 5 200 f
i
+∑(f
o
C
L
) × V
DD
2
f
o
= output freq. (MHz)
C
L
= load cap. (pF)
∑ (f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
V
DD
V
SYMBOL MIN. TYP. MAX.
TYPICAL EXTRAPOLATION
FORMULA