Datasheet

January 1995 3
Philips Semiconductors Product specification
12-stage binary counter
HEF4040B
MSI
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
=25°C; C
L
= 50 pF; input transition times ≤ 20 ns
V
DD
V
SYMBOL MIN. TYP. MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
CP → O
0
5 105 210 ns 78 ns + (0,55 ns/pF) C
L
HIGH to LOW 10 t
PHL
45 90 ns 34 ns + (0,23 ns/pF) C
L
15 35 70 ns 27 ns + (0,16 ns/pF) C
L
5 85 170 ns 58 ns + (0,55 ns/pF) C
L
LOW to HIGH 10 t
PLH
40 80 ns 29 ns + (0,23 ns/pF) C
L
15 30 60 ns 22 ns + (0,16 ns/pF) C
L
O
n
→ O
n + 1
5 35 70 ns note 1 (0,55 ns/pF) C
L
HIGH to LOW 10 t
PHL
15 30 ns note 1 (0,23 ns/pF) C
L
15 10 20 ns note 1 (0,16 ns/pF) C
L
5 35 70 ns note 1 (0,55 ns/pF) C
L
LOW to HIGH 10 t
PLH
15 30 ns note 1 (0,23 ns/pF) C
L
15 10 20 ns note 1 (0,16 ns/pF) C
L
MR → O
n
5 90 180 ns 63 ns + (0,55 ns/pF) C
L
HIGH to LOW 10 t
PHL
40 80 ns 29 ns + (0,23 ns/pF) C
L
15 30 60 ns 22 ns + (0,16 ns/pF) C
L
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
L
HIGH to LOW 10 t
THL
30 60 ns 9 ns + (0,42 ns/pF) C
L
15 20 40 ns 6 ns + (0,28 ns/pF) C
L
5 60 120 ns 10 ns + (1,0 ns/pF) C
L
LOW to HIGH 10 t
TLH
30 60 ns 9 ns + (0,42 ns/pF) C
L
15 20 40 ns 6 ns + (0,28 ns/pF) C
L
Fig.3 Logic diagram.