Datasheet
January 1995 2
Philips Semiconductors Product speciļ¬cation
8-bit static shift register
HEF4021B
MSI
DESCRIPTION
The HEF4021B is an 8-bit static shift register
(parallel-to-serial converter) with a synchronous serial
data input (D
S
), a clock input (CP), an asynchronous active
HIGH parallel load input (PL), eight asynchronous parallel
data inputs (P
0
to P
7
) and buffered parallel outputs from
the last three stages (0
5
to O
7
).
Each register stage is a D-type master-slave flip-flop with
a set direct/clear direct input. Information on P
0
to P
7
is
asynchronously loaded into the register while PL is HIGH,
independent of CP and DS. When PL is LOW, data on
D
S
is shifted into the first register position and all the data
in the register is shifted one position to the right on the
LOW to HIGH transition of CP. Schmitt-trigger action in the
clock input makes the circuit highly tolerant to slower clock
rise and fall times.
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
HEF4021BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4021BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4021BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
PINNING
PL parallel load input
P
0
to P
7
parallel data inputs
D
S
serial data input
CP clock input (LOW to HIGH edge-triggered)
O
5
to O
7
buffered parallel outputs from the last three stages