Datasheet

HEF4017B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 18 November 2011 3 of 18
NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 3. Logic symbol Fig 4. IEE logic symbol
Q9
Q5-9
11
12
Q8 9
MR15
14
13
CP0
CP1
Q7 6
Q6
Q5 1
5
Q4
Q3 7
10
Q2 4
Q1 2
Q0 3
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9
CT≥5
11
12
8
9
CT = 0
CTRDIV10/DEC
15
13
14
7
6
6
5
1
5
4
3
7
10
2
4
1
2
0
3
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&
Fig 5. Pin configuration
HEF4017B
Q5 V
DD
Q1 MR
Q0 CP0
Q2 CP1
Q6 Q5-9
Q7 Q9
Q3 Q4
V
SS
Q8
001aae574
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
Q0 to Q9 3, 2, 4, 7, 10, 1, 5, 6, 9, 11 decoded output
V
SS
8 ground supply voltage
Q
5-9 12 carry output (active LOW)
CP
1 13 clock input (HIGH-to-LOW edge-triggered)