Datasheet

HEF4017B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 18 November 2011 11 of 18
NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
12. Application information
Some examples of applications for the HEF4017B are:
• Decade counter with decimal decoding
• 1 out of n decoding counter (when cascaded)
• Sequential controller
• Timer
Figure 11
shows a technique for extending the number of decoded output states for the
HEF4017B. Decoded outputs are sequential within each stage and from stage to stage,
with no dead time (except propagation delay).
a. Input waveforms
b. Test circuit
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test;
C
L
= load capacitance including jig and probe capacitance;
R
T
= termination resistance should be equal to the output impedance Z
o
of the pulse generator.
Fig 10. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
90 %
10 %
t
f
t
r
t
r
t
f
001aaj781
V
DD
V
I
V
O
001aag182
DUT
C
L
R
T
G
Table 10. Test data
Supply voltage Input Load
V
DD
V
I
t
r
, t
f
C
L
5 V to 15 V V
SS
or V
DD
 20 ns 50 pF