Datasheet

HEF4017B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 18 November 2011 10 of 18
NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
Conditions: CP1 = LOW, while CP0 triggers on a LOW-to-HIGH transition, t
W
and t
rec
are measured when CP0 = HIGH and
CP
1 triggers on a HIGH-to-LOW transition.
The shaded areas indicate where the output state is set by the input count.
Measurement points given in Tabl e 9
.
Fig 8. Waveforms showing the minimum pulse width for CP0, CP1 and MR input; the maximum frequency for
CP0 and CP
1 input; the recovery time for MR and the MR input to Qn and Q5-9 output propagation delays
CP0 input
V
I
V
SS
V
I
V
SS
V
I
V
SS
V
OH
V
OL
V
OH
V
OL
Q1 - Q9
output
MR input
CP1 input
V
M
V
M
1/f
max
t
W
t
W
t
rec
V
M
1/f
max
t
W
t
PLH
t
PHL
V
M
V
M
001aaj306
Q0, Q5 - Q9
output
Hold times are shown as positive values, but may be specified as negative values;
Measurement points given in Tabl e 9
.
Fig 9. Waveforms showing hold times for CP0 to CP1 and CP1 to CP0
001aae578
CP0 input
V
I
V
SS
V
I
V
SS
CP1 input
t
h
V
M
V
M
V
M
t
h
V
M
Table 9. Measurement points
Supply voltage Input Output
V
DD
V
M
V
M
5 V to 15 V 0.5V
DD
0.5V
DD