Datasheet

NXP Semiconductors
KTFRDMPF1550EVMUG
FRDM-PF1550EVM evaluation board
KTFRDMPF1550EVMUG All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
User guide Rev. 2.0 — 7 March 2018
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5.3 Device features
The evaluation board feature the following NXP product:
Table 1. Device features
Device Description Features
PF1550 Power management integrated circuit
(PMIC) for i.MX 7ULP, i.MX 6SL, 6UL,
6ULL and 6SX processors
• Three adjustable high efficiency buck regulators
with 1.0 A per regulator current capability
• Three adjustable general purpose linear regulators
• Battery charger (JEITA compliant battery temp.
sensing)
• Input voltage range on VBUSIN: 4.1 V to 6.0 V
• LDO/switch supply
• DDR memory reference voltage
• One time programmable (OTP) memory for device
configuration
5.3.1 Device description
The PF1550 device populated on board features the A4 OTP. See Table 2.
Table 2. Startup configuration
Register Pre-programmed OTP configuration – A4
configuration
OTP_VSNVS_VOLT[2:0] 3.0 V
OTP_SW1_VOLT[5:0] 1.1 V
OTP_SW1_PWRUP_SEQ[2:0] 4
OTP_SW2_VOLT[5:0] 1.2 V
OTP_SW2_PWRUP_SEQ[2:0] 3
OTP_SW3_VOLT[5:0] 1.8 V
OTP_SW3_PWRUP_SEQ[2:0] 2
OTP_LDO1_VOLT[4:0] 3.3 V
OTP_LDO1_PWRUP_SEQ[2:0] 1
OTP_LDO2_VOLT[3:0] 3.3 V
OTP_LDO2_PWRUP_SEQ[2:0] 2
OTP_LDO3_VOLT[4:0] 1.8 V
OTP_LDO3_PWRUP_SEQ[2:0] 1
OTP_VREFDDR_PWRUP_SEQ[2:0] 3
OTP_SW1_DVS_ENB DVS mode
OTP_SW2_DVS_ENB DVS mode
OTP_LDO1_LS_EN LDO mode
OTP_LDO3_LS_EN LDO mode
OTP_SW1_RDIS_ENB Enabled
OTP_SW2_RDIS_ENB Enabled
OTP_SW3_RDIS_ENB Enabled
OTP_SW1_DVSSPEED 12.5 mV step each 4.0 μs
OTP_SW2_DVSSPEED 12.5 mV step each 4.0 μs