Datasheet

NOTE
• Numbers are for a load of 15pf (1.8V) and 35pf (3V)
• The numbers are for setting of hold condition in register
QuadSPI_SMPR[DDRSNP]
Table 63. QuadSPI input timing (DDR mode) specifications
Symbol Parameter Value Unit
Min Max
T
is
Setup time for incoming data 4 (Without
learning)
— ns
1 (With
learning)
—
T
ih
Hold time requirement for incoming data 1.5 — ns
1 2 3
Tck
Tcss Tcsh
Tov
Toh
Clock
SFCK
CS
Data out
Figure 26. QuadSPI output timing (DDR mode) diagram
Table 64. QuadSPI output timing (DDR mode) specifications
Symbol Parameter Value Unit
Min Max
T
ov
Output Data Valid — 4.5 ns
T
oh
Output Data Hold 1.5 — ns
T
ck
SCK clock period — 72 (with learning) MHz
— 45 (without learning)
T
css
Chip select output setup time 2 — Clk(sck)
T
csh
Chip select output hold time -1 — Clk(sck)
Hyperflash mode
Electrical characteristics
98
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
NXP Semiconductors