Datasheet

1 2 3
Toh
Tov
Tck
Tcss Tcsh
Clock
SFCK
CS
Data out
Figure 24. QuadSPI output timing (SDR mode) diagram
Table 62. QuadSPI output timing (SDR mode) specifications
Symbol Parameter Value Unit
Min Max
T
ov
Output Data Valid — 2.8 ns
T
oh
Output Data Hold -1.4 — ns
T
ck
SCK clock period — 96 MHz
T
css
Chip select output setup time 2 — ns
T
csh
Chip select output hold time -1 — ns
NOTE
For any frequency setup and hold specifications of the
memory should be met.
DDR Mode
1 2 3
Tck
Tcss Tcsh
Tis
Tih
Clock
SFCK
CS
Data in
Figure 25. QuadSPI input timing (DDR mode) diagram
Electrical characteristics
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
97
NXP Semiconductors