Datasheet

1 2 3
Tck
Tcss Tcsh
Tis
Tih
Clock
SFCK
CS
Data in
Figure 23. QuadSPI input timing (SDR mode) diagram
NOTE
• The below timing values are with default settings for
sampling registers like QuadSPI_SMPR.
• A negative time indicates the actual capture edge inside
the device is earlier than clock appearing at pad.
• The below timing are for a load of 15pf (1.8V) and 35pf
(3V) or output pads
• All board delays need to be added appropriately
• Input hold time being negative does not have any
implication or max achievable frequency
Table 61. QuadSPI input timing (SDR mode) specifications
Symbol Parameter Value Unit
Min Max
T
is
Setup time for incoming data 4 — ns
T
ih
Hold time requirement for incoming data 1.5 — ns
Electrical characteristics
96
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
NXP Semiconductors