Datasheet

Table 54. MCG specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
J
cyc_pll
PLL period jitter (RMS)
• f
vco
= 180 MHz
• f
vco
= 360 MHz
—
—
120
75
—
—
ps
ps
9
J
acc_pll
PLL accumulated jitter over 1µs (RMS)
• f
vco
= 180 MHz
• f
vco
= 360 MHz
—
—
1350
600
—
—
ps
ps
9
D
unl
Lock exit frequency tolerance ±4.47 — ±5.97 %
t
pll_lock
Lock detector detection time — — 150 × 10
-6
+ 1075(1/
f
pll_ref
)
s 10
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. This applies when SCTRIM at value (0x80) and SCFTRIM control bit at value (0x0).
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (Δf
dco_t
) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
5.4.2.2 IRC48M specifications
Table 55. IRC48M specifications
Symbol Description Min. Typ. Max. Unit Notes
V
DD
Supply voltage 1.71 — 3.6 V
I
DD48M
Supply current — 520 — μA
f
irc48m
Internal reference frequency — 48 — MHz
Δf
irc48m_ol_lv
Open loop total deviation of IRC48M frequency at
low voltage (VDD=1.71V-1.89V) over temperature
• Regulator disable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=0)
• Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
—
—
± 0.5
± 0.5
± 1.5
± 1.5
%f
irc48m
Δf
irc48m_ol_hv
Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over temperature
— ± 0.5 ± 1.5 %f
irc48m
Table continues on the next page...
Electrical characteristics
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
91
NXP Semiconductors