Datasheet

5.3.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO,
LPUART, timers, and I
2
C signals.
Table 50. General switching specifications
Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter disabled) —
Synchronous path
1.5 — Bus clock
cycles
1
GPIO pin interrupt pulse width (digital glitch filter disabled, analog
filter enabled) — Asynchronous path
16
2
— ns 3
GPIO pin interrupt pulse width (digital glitch filter disabled, analog
filter disabled) — Asynchronous path
50 — ns 3
External reset pulse width (digital glitch filter disabled) 100 — ns 3
Port rise and fall time
(high drive) — slew
enabled
1.71 V < V
DDIO_E
< 2.7 V — 34 ns 4, 5
2.7 V < V
DDIO_E
≤ 3.6 V — 16
Port rise and fall time
(high drive) — slew
disabled
1.71 V < V
DDIO_E
< 2.7 V — 4.5 ns 4, 5
2.7 V < V
DDIO_E
≤ 3.6V — 3
Port rise and fall time (low
drive) — slew enabled
1.71 V < V
DDIO_E
< 2.7 V — 25 ns 6, 5
2.7 V < V
DDIO_E
≤ 3.6 V — 16
Port rise and fall time
(high drive) — slew
disabled
1.71 V < V
DDIO_E
< 2.7 V — 4.2 ns 6, 5
2.7 V < V
DDIO_E
≤ 3.6V — 2.5
Port rise and fall time (low
drive) — slew enabled
1.71 < V
DDIO_E
< 2.7V — 25 ns 6, 7
2.7 < V
DDIO_E
≤ 3.6V — 13
Port rise and fall time (low
drive) — slew disabled
1.71 < V
DDIO_E
< 2.7V — 5.5 ns 6, 7
2.7 < V
DDIO_E
≤ 3.6V — 3.5
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75 pF load
5. This is applicable for Port E pins
6. 25 pF load
7. This is applicable for Ports A, B, C, and D.
5.3.4 Thermal specifications
Electrical characteristics
84
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
NXP Semiconductors