Datasheet

Table 2. AWIC Partial Stop, Stop and VLPS wake-up sources

Wake-up source Description

Available system resets RESET_b pin and WDOG when LPO is its clock source, and Debug

Low-voltage detect Power mode controller

Low-voltage warning Power mode controller

Pin interrupts Port control module - any enabled pin interrupt is capable of waking the system

ADC0 The ADC is functional when using internal clock source

CMPx Since no system clocks are available, functionality is limited, trigger mode provides wakeup

functionality with periodic sampling

I2Cx Address match wakeup

LPUARTx Functional when using clock source which is active in Stop and VLPS modes

USB FS/LS Controller Wakeup

FlexIO0 Functional when using clock source which is active in Stop and VLPS modes

LPTMR Functional when using clock source which is active in Stop, VLPS and LLS/VLLS modes

RTC Functional in Stop/VLPS modes

TPM Functional when using clock source which is active in Stop and VLPS modes

TSI0 Wakeup

NMI Non-maskable interrupt

2.1.4 Memory

This device has the following features:

• 96 KB of embedded RAM accessible (read/write) at CPU clock speed with 0 wait

states.

• The non-volatile memory is divided into two arrays

• 128 KB of embedded program memory

• 32 KB ROM (built-in bootloader to support UART, I2C, USB, and SPI

interfaces)

The program flash memory contains a 16-byte flash configuration field that stores

default protection settings and security information. The page size of program flash

is 1 KB.

The protection setting can protect 32 regions of the program flash memory from

unintended erase or program operations.

The security circuitry prevents unauthorized access to RAM or flash contents from

debug port.

• System register file

Overview

Kinetis KL82 Microcontroller, Rev. 3, 08/2016

NXP Semiconductors