Datasheet

5.3.2.4 Power mode transition operating behaviors
All specifications except t
POR
, and VLLSx –> RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 72 MHz
• Bus clock = 24 MHz
• Flash clock = 24 MHz
• MCG mode=FEI
Table 45. Power mode transition operating behaviors
Symbol Description Min. Max. Unit Notes
t
POR
After a POR event, amount of time
from the point V
DD
reaches 1.71 V
to execution of the first instruction
across the operating temperature
range of the chip.
V
DD
slew rate ≥ 5.7
kV/s
— 300 µs 1
V
DD
slew rate < 5.7
kV/s
— 1.7 V/
(V
DD
slew
rate)
• VLLS0 –> RUN
— 138 µs
• VLLS1 –> RUN
— 138 µs
• VLLS2 –> RUN
— 76 µs
• VLLS3 –> RUN
— 76 µs
• LLS2 –> RUN
— 6.1 µs
• LLS3 –> RUN
— 6.1 µs
• VLPS –> RUN
— 5.6 µs
• STOP –> RUN
— 5.6 µs
1. Normal boot (FTFA_FOPT[LPBOOT]=1)
Table 46. Low power mode peripheral adders — typical value
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
1
I
IREFSTEN4MHz
4 MHz internal reference clock (IRC) adder.
Measured by entering STOP or VLPS mode
with 4 MHz IRC enabled.
56 56 56 56 56 56 µA
I
IREFSTEN32KHz
32 kHz internal reference clock (IRC) adder.
Measured by entering STOP mode with the
32 kHz IRC enabled.
52 52 52 52 52 52 µA
Table continues on the next page...
Electrical characteristics
72
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
NXP Semiconductors