Datasheet

GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
ADC0(16-bit 16-ch)
CMP0
1.2V Voltage reference
TPM0(6-channel)
TPM1(2-channel)
TPM2(2-channel)
LPTMR0
PIT0
RTC
LPUART0
LPUART1
LPUART2
SPI0
SPI1
I2C0
I2C1
FlexIO0
Watchdog
Register File(32 Bytes)
CRC
LLWU
RCM
SMC
PMC
96 KB
RAM
32 KB ROM
FMC
BME
DMA
MUX
DMA
Debug
(SWD)
IOPORT
IRC 48M
IRC 4MHz
OSC
128 KB
Flash
Cortex M0+
USB FS/LS
CM0+ core
Crossbar switch
M0
M2
M3
S2b
S1
S0
Master
Slave
Peripheral Bridge(Bus Clock - Max 24MHZ)
NVIC
MCG
System memory protection unit (MPU)
S2a
2 KB
USB SRAM
RTC OSC
IRC 32kHz
FLL
PLL
S3
QSPI0
Bit
Band
LPTMR1
EWM
LP Trusted Cryptographic 0
TRNG0
VBAT Register File(128B)
TSI0
EMVSIM0
EMVSIM1
INTMUX0
Figure 1. System diagram
The crossbar switch connects bus masters and slaves using a crossbar switch structure.
This structure allows up to four bus masters to access different bus slaves
simultaneously, while providing arbitration among the bus masters when they access
the same slave.
Overview
6
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
NXP Semiconductors