Datasheet

Table 30. SPI1 signal descriptions
Chip signal name Module signal
name
Description I/O
SPI1_PCS0 PCS0/SS Peripheral Chip Select 0 (O) in the master mode and Slave
Select (I) in the slave mode
I/O
SPI1_PCS[1:3] PCS[1:3] Peripheral Chip Selects 1–3 in the master mode O
SPI1_SIN SIN Serial Data In I
SPI1_SOUT SOUT Serial Data Out O
SPI1_SCK SCK Serial Clock (O) in the master mode and Serial Clock (I) in the
slave mode
I/O
Table 31. I2C0 signal descriptions
Chip signal name Module signal
name
Description I/O
I2C0_SCL SCL Bidirectional serial clock line of the I2C system. I/O
I2C0_SDA SDA Bidirectional serial data line of the I2C system. I/O
Table 32. I2C1 signal descriptions
Chip signal name Module signal
name
Description I/O
I2C1_SCL SCL Bidirectional serial clock line of the I2C system. I/O
I2C1_SDA SDA Bidirectional serial data line of the I2C system. I/O
Table 33. LPUART0 signal descriptions
Chip signal name Module signal
name
Description I/O
LPUART0_CTS_b LPUART_CTS Clear to Send I
LPUART0_RTS_b LPUART_RTS Request to send O
LPUART0_TX LPUART_TX Transmit data. This pin is normally an output, but is an input
(tristated) in single wire mode whenever the transmitter is
disabled or transmit direction is configured for receive data.
I/O
LPUART0_RX LPUART_RX Receive Data I
Table 34. LPUART1 signal descriptions
Chip signal name Module signal
name
Description I/O
LPUART1_CTS_b LPUART_CTS Clear to Send I
LPUART1_RTS_b LPUART_RTS Request to send O
Table continues on the next page...
Pinouts
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
49
NXP Semiconductors