Datasheet

Table 27. TPM2 Signal Descriptions
Chip signal name Module signal
name
Description I/O
TPM_CLKIN[1:0] TPM_EXTCLK External clock. TPM external clock can be selected to increment
the TPM counter on every rising edge synchronized to the counter
clock.
I
TPM1_CH[1:0] TPM_CHn A TPM channel pin is configured as output when configured in an
output compare or PWM mode and the TPM counter is enabled,
otherwise the TPM channel pin is an input.
I/O
4.3.7 Communication interfaces
Table 28. USB FS OTG signal descriptions
Chip signal name Module signal
name
Description I/O
USB0_DM usb_dm USB D- analog data signal on the USB bus. I/O
USB0_DP usb_dp USB D+ analog data signal on the USB bus. I/O
USB0_CLKIN — Alternate USB clock input I
USB_VDD — USB domain power supply, 3.3 V. I
USB0_SOF_OUT — USB start of frame signal. Can be used to make the USB start of
frame available for external synchronization.
O
Table 29. SPI0 signal descriptions
Chip signal name Module signal
name
Description I/O
SPI0_PCS0 PCS0/SS Peripheral Chip Select 0 (O) in the master mode and Slave Select
(I) in the slave mode
I/O
SPI0_PCS[1:3] PCS[1:3] Peripheral Chip Selects 1–3 in the master mode O
SPI0_PCS4 PCS4 Peripheral Chip Select 4 in the master mode O
SPI0_PCS5 PCS5 Peripheral Chip Select 5 /Peripheral Chip Select Strobe in the
master mode
O
SPI0_SIN SIN Serial Data In I
SPI0_SOUT SOUT Serial Data Out O
SPI0_SCK SCK Serial Clock (O) in the master mode and Serial Clock (I) in the
slave mode
I/O
Pinouts
48
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
NXP Semiconductors