Datasheet

4.3.5 Analog
Table 18. ADC0 Signal Descriptions
Chip signal name Module signal
name
Description I/O
ADC0_DP[1:0] DADP1–DADP0 Differential analog channel inputs I
ADC0_DM[1:0] DADM1–DADM0 Differential Analog Channel Inputs I
ADC0_SEn ADn Single-Ended Analog Channel Inputs
1
I
VREFH V
REFSH
Voltage Reference Select High I
VREFL V
REFSL
Voltage Reference Select Low I
VDDA V
DDA
Analog power supply I
VSSA V
SSA
Analog ground I
1. See ADC channel assignment for the n.
Table 19. CMP0 Signal Descriptions
Chip signal name Module signal
name
Description I/O
CMP0_INn, n=[5,3:0] INn, n=[5,3:0] Analog voltage inputs, see CMP input connection for more details
about the n.
I
CMP0_OUT CMPO Comparator output O
NOTE
There is no CMP0_IN[4] coming from pad.
Table 20. DAC0 Signal Descriptions
Chip signal name Module signal
name
Description I/O
DAC0_OUT — DAC output O
Table 21. VREF Signal Descriptions
Chip signal name Module signal
name
Description I/O
VREF_OUT VREF_OUT Internally-generated Voltage Reference output O
Pinouts
46
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
NXP Semiconductors