Datasheet

121
MAP
BGA
100
LQFP
80
LQFP
64
MAP
BGA
64
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
E7 61 — — — VDD VDD VDD
B10 62 51 — — PTB16 TSI0_CH9 TSI0_CH9 PTB16 SPI1_SOUT LPUART0_
RX
TPM_
CLKIN0
EWM_IN
E9 63 52 — — PTB17 TSI0_CH10 TSI0_CH10 PTB17 SPI1_SIN LPUART0_
TX
TPM_
CLKIN1
EWM_OUT_
b
D9 64 53 D6 41 PTB18 TSI0_CH11 TSI0_CH11 PTB18 TPM2_CH0 FXIO0_D6
C9 65 54 C7 42 PTB19 TSI0_CH12 TSI0_CH12 PTB19 TPM2_CH1 FXIO0_D7
F10 66 — — — PTB20 DISABLED PTB20 CMP0_OUT FXIO0_D8
F9 67 — — — PTB21 DISABLED PTB21 FXIO0_D9
F8 68 — — — PTB22 DISABLED PTB22 FXIO0_D10
E8 69 — — — PTB23 DISABLED PTB23 SPI0_PCS5 FXIO0_D11
B9 70 55 D8 43 PTC0 ADC0_
SE14/
TSI0_CH13
ADC0_
SE14/
TSI0_CH13
PTC0 SPI0_PCS4 EXTRG_IN USB0_
SOF_OUT
FXIO0_D12
D8 71 56 C6 44 PTC1/
LLWU_P6
ADC0_
SE15/
TSI0_CH14
ADC0_
SE15/
TSI0_CH14
PTC1/
LLWU_P6
SPI0_PCS3 LPUART1_
RTS_b
TPM0_CH0 FXIO0_D13
C8 72 57 B7 45 PTC2 ADC0_
SE4b/
TSI0_CH15
ADC0_
SE4b/
TSI0_CH15
PTC2 SPI0_PCS2 LPUART1_
CTS_b
TPM0_CH1
B8 73 58 C8 46 PTC3/
LLWU_P7
DISABLED PTC3/
LLWU_P7
SPI0_PCS1 LPUART1_
RX
TPM0_CH2 CLKOUT
— 74 59 E3 47 VSS VSS VSS
— 75 60 E4 48 VDD VDD VDD
A8 76 61 B8 49 PTC4/
LLWU_P8
DISABLED PTC4/
LLWU_P8
SPI0_PCS0 LPUART1_
TX
TPM0_CH3
D7 77 62 A8 50 PTC5/
LLWU_P9
DISABLED PTC5/
LLWU_P9
SPI0_SCK LPTMR0_
ALT2/
LPTMR1_
ALT2
CMP0_OUT TPM0_CH2
C7 78 63 A7 51 PTC6/
LLWU_P10
CMP0_IN0 CMP0_IN0 PTC6/
LLWU_P10
SPI0_SOUT EXTRG_IN FXIO0_D14
B7 79 64 B6 52 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN USB0_
SOF_OUT
FXIO0_D15
A7 80 65 A6 53 PTC8 CMP0_IN2 CMP0_IN2 PTC8 FXIO0_D16
D6 81 66 B5 54 PTC9 CMP0_IN3 CMP0_IN3 PTC9 FXIO0_D17
C6 82 67 B4 55 PTC10 DISABLED PTC10 I2C1_SCL FXIO0_D18
C5 83 68 A5 56 PTC11/
LLWU_P11
DISABLED PTC11/
LLWU_P11
I2C1_SDA FXIO0_D19
B6 84 69 — — PTC12 DISABLED PTC12 TPM_
CLKIN0
A6 85 70 — — PTC13 DISABLED PTC13 TPM_
CLKIN1
A5 86 — — — PTC14 DISABLED PTC14 FXIO0_D20
Pinouts
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
35
NXP Semiconductors