Datasheet

4 Pinouts
4.1 KL82 signal multiplexing and pin assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
121
MAP
BGA
100
LQFP
80
LQFP
64
MAP
BGA
64
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
B1 1 1 A1 1 PTE0 DISABLED PTE0 SPI1_PCS1 LPUART1_
TX
QSPI0A_
DATA3
I2C1_SDA RTC_
CLKOUT
C2 2 2 B1 2 PTE1/
LLWU_P0
DISABLED PTE1/
LLWU_P0
SPI1_SCK LPUART1_
RX
QSPI0A_
SCLK
I2C1_SCL SPI1_SIN
C1 3 3 C5 3 PTE2/
LLWU_P1
DISABLED PTE2/
LLWU_P1
SPI1_SOUT LPUART1_
CTS_b
QSPI0A_
DATA0
SPI1_SCK
D2 4 4 D2 4 PTE3 DISABLED PTE3 SPI1_PCS2 LPUART1_
RTS_b
QSPI0A_
DATA2
SPI1_SOUT
F7 5 5 C4 5 VSS VSS VSS
E5 6 6 D3 6 VDDIO_E VDDIO_E VDDIO_E
D1 7 7 E2 7 PTE4/
LLWU_P2
DISABLED PTE4/
LLWU_P2
SPI1_SIN QSPI0A_
DATA1
E2 8 8 D1 8 PTE5 DISABLED PTE5 SPI1_PCS0 QSPI0A_
SS0_B
USB0_
SOF_OUT
E1 9 — — — PTE6/
LLWU_P16
DISABLED PTE6/
LLWU_P16
SPI1_PCS3 QSPI0B_
DATA3
F3 10 9 — — PTE7 DISABLED PTE7 QSPI0B_
SCLK
QSPI0A_
SS1_B
F2 11 10 — — PTE8 DISABLED PTE8 QSPI0B_
DATA0
F1 12 — — — PTE9/
LLWU_P17
DISABLED PTE9/
LLWU_P17
QSPI0B_
DATA2
G2 13 — — — PTE10/
LLWU_P18
DISABLED PTE10/
LLWU_P18
QSPI0B_
DATA1
G1 14 11 — — PTE11 DISABLED PTE11 QSPI0B_
SS0_B
QSPI0A_
DQS
— 15 12 — — VDDIO_E VDDIO_E VDDIO_E
— 16 13 — 9 VSS VSS VSS
H3 — — F3 — VSS VSS VSS
H2 17 14 E1 10 USB0_DP USB0_DP USB0_DP
H1 18 15 F1 11 USB0_DM USB0_DM USB0_DM
Pinouts
32
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
NXP Semiconductors