Datasheet

• High sensitivity change with 16-bit resolution register

• Configurable up to 4096 scan times.

• Support DMA data transfer

2.2.21 QuadSPI

The Quad Serial Peripheral Interface (QuadSPI) block acts as an interface to one single

or two external serial flash devices, each with up to eight bidirectional data lines. This

device contains one QSPI module, which supports singles, dual, quad or octal data lines

in single (SDR) or double (DDR) data rate configurations. The QuadSPI clock

frequencies support up to 96 MHz in SDR mode and up to 72 MHz in DDR mode.

The QuadSPI has the following features:

• Flexible sequence engine to support various flash vendor devices.

• Single, dual, quad and octal modes of operation.

• DDR/DTR mode wherein the data is generated on every edge of the serial flash

clock.

• Support for flash data strobe signal for data sampling in DDR and SDR mode.

• Support for parallel writes via register mapped interface in single I/O mode.

• Two identical serial flash devices can be connected and accessed in parallel for data

read operations, forming one (virtual) flash memory with doubled readout

bandwidth.

• DMA support to read RX Buffer data via AMBA AHB bus (64-bit width interface)

or IP registers space (32-bit access) and DMA support to fill TX Buffer via IPS

• Multimaster accesses with priority

• Multiple interrupt conditions

• Memory mapped read access to connected flash devices.

• Programmable sequence engine to cater to future command/protocol changes and

able to support all existing vendor commands and operations.

Memory map

This device contains various memories and memory-mapped peripherals which are

located in a 4 GB memory space. The following figure shows the system memory and

peripheral locations

Memory map

Kinetis KL82 Microcontroller, Rev. 3, 08/2016

NXP Semiconductors