Datasheet

• Programmable baud rates (13-bit modulo divider) with configurable oversampling

ratio from 4x to 32x

• Transmit and receive baud rate can operate asynchronous to the bus clock

• Interrupt, DMA or polled operation

• Hardware parity generation and checking

• Programmable 8-bit, 9-bit or 10-bit character length

• Programmable 1-bit or 2-bit stop bits

• Three receiver wakeup methods: idle line wakeup, address mark wakeup, receive

data match

• Automatic address matching to reduce ISR overhead

• Optional 13-bit break character generation / 11-bit break character detection

• Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle

characters

• Selectable transmitter output and receiver input polarity

• Hardware flow control support for request to send (RTS) and clear to send (CTS)

signals

• Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable

pulse width

2.2.12

SPI

This device contains two SPI modules. SPI modules support 8-bit and 16-bit modes.

FIFO function is available only on SPI1 module.

The SPI modules have the following features:

• Full-duplex or single-wire bidirectional mode

• Programmable transmit bit rate

• Double-buffered transmit and receive data register

• Serial clock phase and polarity options

• Slave select output

• Mode fault error flag with CPU interrupt capability

• Control of SPI operation during wait mode

• Selectable MSB-first or LSB-first shifting

• Programmable 8- or 16-bit data transmission length

• Receive data buffer hardware match feature

• 64-bit FIFO mode for high speed/large amounts of data transfers

• Support DMA

Overview

Kinetis KL82 Microcontroller, Rev. 3, 08/2016

NXP Semiconductors