Datasheet

• Bandgap on only, used for stabilization and startup

• High power buffer mode

• Low-power buffer mode

• Buffer disabled

A 100 nF capacitor must always be connected between VERF output (VREFO) pin and

VSSA if the VREF is used. This capacitor must be as close to VREFO pin as possible.

2.2.6 CMP

The device contains one high-speed comparator and two 8-input multiplexers for both

the inverting and non-inverting inputs of the comparator. Each CMP input channel

connects to both muxes.

The CMP includes one 6-bit DAC, which provides a selectable voltage reference for

various user application cases. Besides, the CMP also has several module-to-module

interconnects in order to facilitate ADC triggering, TPM triggering, and interfaces.

The CMP has the following features:

• Inputs may range from rail to rail

• Programmable hysteresis control

• Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of

the comparator output

• Selectable inversion on comparator output

• Capability to produce a wide range of outputs such as sampled, digitally filtered

• External hysteresis can be used at the same time that the output filter is used for

internal functions

• Two software selectable performance levels: shorter propagation delay at the

expense of higher power and Low power with longer propagation delay

• DMA transfer support

• Functional in all modes of operation except in VLLS0 mode

• The window and filter functions are not available in Stop, VLPS, LLS, or VLLSx

modes

• Integrated 6-bit DAC with selectable supply reference source and can be power

down to conserve power

• Two 8-to-1 channel mux

Overview

Kinetis KL82 Microcontroller, Rev. 3, 08/2016

NXP Semiconductors