Datasheet

2.2.2 eDMA and DMAMUX
The eDMA controller module enables fast transfers of data, which provides an efficient
way to move blocks of data with minimal processor interaction. The eDMA controller
in this device implements eight channels which can be routed from up to 63 DMA
request sources through DMA MUX module. Some of the peripheral request sources
have asynchronous eDMA capability which can be used to wake MCU from Stop
mode. The peripherals which have such capability include FlexIO, LPUART0,
LPUART1, LPUART2, TPM0, TPM1, TPM2, PORTA-PORTE, ADC0, and CMP0.
The DMA channel 0 t0 3 can be periodically triggered by PIT via DMA MUX.
Main features are listed below:
• Dual-address transfers via 32-bit master connection to the system bus and data
transfers in 8-, 16-, or 32-bit blocks
• 8-channel implementation that performs complex data transfers with minimal
intervention from a host processor
• Transfer control descriptor (TCD) organized to support two-deep, nested transfer
operations
• Provide the selectable channel activation methods.
• Fixed-priority and round-robin channel arbitration
• Channel completion reported via programmable interrupt requests
• Programmable support for scatter/gather DMA processing
• Support for complex data structures
2.2.3
TPM
This device contains three low power TPM modules (TPM). All TPM modules are
functional in Stop/VLPS mode if the clock source is enabled.
The TPM features include:
• TPM clock mode is selectable from external clock input or internal clock source,
HIRC48M clock, external crystal input clock, MCGIRCLK, MCGPLLCLK, or
MCGFLLCLK.
• Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128
• TPM includes a 16-bit counter
• Includes 6 channels that can be configured for input capture, output compare, edge-
aligned PWM mode, or center-aligned PWM mode
• Support the generation of an interrupt and/or DMA request per channel or counter
overflow
Overview
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Kinetis KL82 Microcontroller, Rev. 3, 08/2016
NXP Semiconductors