Datasheet

Table 7. Wakeup sources for LLWU inputs (continued)

LLWU pins Module sources or pin names

LLWU_M1IF CMP0

LLWU_M2IF Reserved

LLWU_M3IF Reserved

LLWU_M4IF TSI0

LLWU_M5IF RTC alarm

LLWU_M6IF Reserved

LLWU_M7IF RTC second

1. A wakeup source of LLWU, USB0_DP or USB0_DM is available only when the chip is in USB host mode.

2. Requires the peripheral and the peripheral interrupt to be enabled. The LLWU_ME[WUMEn] (n=0-7) bit enables the

internal module flag a wakeup inputs. After wakeup, the flags are cleared based on the peripheral clearing mechanism.

2.1.10 Debug controller

This device supports standard ARM 2-pin SWD debug port. It provides register and

memory accessibility from the external debugger interface, basic run/halt control plus 2

breakpoints and 2 watchpoints.

It also supports trace function with the Micro Trace Buffer (MTB), which provides a

simple execution trace capability for the Cortex-M0+ processor.

2.1.11

INTMUX

The Interrupt Multiplexer (INTMUX) routes the interrupt sources to the interrupt

outputs. It provides interrupt status registers to monitor interrupt pending status and

vector numbers and implements the ability to logical AND or OR enabled interrupts on

a given channel.

The INTMUX has the following features:

• Supports 4 multiplex channels

• Each channel receives 32 interrupt sources and has one interrupt output

• Each interrupt source can be enabled or disabled

• Each channel supports logic AND or logic OR of all enabled interrupt sources

Overview

Kinetis KL82 Microcontroller, Rev. 3, 08/2016

NXP Semiconductors