Datasheet

Table 6. Peripherals states in different operational modes

Core mode Device mode Descriptions

Run mode High Speed Run In HSRun mode, MCU is able to operate at a faster frequency, all device

modules are operational.

Run In Run mode, all device modules are operational.

Very Low Power Run In VLPR mode, all device modules are operational at a reduced frequency

except the Low Voltage Detect (LVD) monitor, which is disabled.

Sleep mode Wait In Wait mode, all peripheral modules are operational. The MCU core is placed

into Sleep mode.

Very Low Power Wait In VLPW mode, all peripheral modules are operational at a reduced frequency

except the Low Voltage Detect (LVD) monitor, which is disabled. The MCU

core is placed into Sleep mode.

Deep sleep Stop In Stop mode, most peripheral clocks are disabled and placed in a static state.

Stop mode retains all registers and SRAMs while maintaining Low Voltage

Detection protection. In Stop mode, the ADC, DAC, CMP, LPTimer, RTC,

TPM, LPUART, TSI and pin interrupts are operational. The NVIC is disabled,

but the AWIC can be used to wake up from an interrupt.

Very Low Power Stop In VLPS mode, the contents of the SRAM are retained. The CMP (low speed),

ADC, OSC, RTC, LPTMR, TPM, FlexIO, LPUART, USB, TSI and DMA are

operational, LVD and NVIC are disabled, AWIC is used to wake up from

interrupt.

Low Leakage Stop In LLS mode, the contents of the SRAM and the 32-byte system register file

are retained. The CMP (low speed), LLWU, LPTMR, and RTC are operational.

The ADC, CRC, DMA, FlexIO, I2C, LPUART, MCG-Lite, NVIC, PIT, SPI, TPM,

UART, USB, and WDOGCOP are static, but retain their programming. The

DAC, GPIO, and VREF are static, retain their programming, and continue to

drive their previous values.

Very Low Leakage Stop In VLLS modes, most peripherals are powered off and will resume operation

from their reset state when the device wakes up. The LLWU, LPTMR, and

RTC are operational in all VLLS modes.

In VLLS3, the contents of the SRAM and the 32-byte system register file are

retained. The CMP (low speed), and PMC are operational. The DAC, GPIO,

and VREF are not operational but continue driving.

In VLLS1, the contents of the 32-byte system register file are retained. The

CMP (low speed), and PMC are operational. The DAC, GPIO, and VREF are

not operational but continue driving.

In VLLS0, the contents of the 32-byte system register file are retained. The

PMC is operational. The GPIO is not operational but continues driving. The

POR detection circuit can be enabled or disabled.

2.1.9 LLWU

The LLWU module is used to wake MCU from low leakage power mode (LLS and

VLLSx) and functional only on entry into a low-leakage power mode. After recovery

from LLS, the LLWU is immediately disabled. After recovery from VLLSx, the LLWU

continues to detect wake-up events until the user has acknowledged the wake-up event.

Overview

Kinetis KL82 Microcontroller, Rev. 3, 08/2016

NXP Semiconductors