Datasheet

Table 88. I2C timing (continued)
Characteristic Symbol Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
Data set-up time t
SU
; DAT 250
5
— 100
3
,
6
— ns
Rise time of SDA and SCL signals t
r
— 1000 20 +0.1C
b
7
300 ns
Fall time of SDA and SCL signals t
f
— 300 20 +0.1C
b
6
300 ns
Set-up time for STOP condition t
SU
; STO 4 — 0.6 — µs
Bus free time between STOP and
START condition
t
BUF
4.7 — 1.3 — µs
Pulse width of spikes that must be
suppressed by the input filter
t
SP
N/A N/A 0 50 ns
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can be achieved only when using the
normal drive pins and VDD ≥ 2.7 V.
2. The master mode I
2
C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I
2
C bus device can be used in a Standard mode I2C bus system, but the requirement t
SU; DAT
≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t
rmax
+ t
SU;
DAT
= 1000 + 250 = 1250 ns (according to the Standard mode I
2
C bus specification) before the SCL line is released.
7. C
b
= total capacitance of the one bus line in pF.
To achieve 1MHz I2C clock rates, consider the following recommendations:
• To counter the effects of clock stretching, the I2C baud Rate select bits can be
configured for faster than desired baud rate.
• Use high drive pad and DSE bit should be set in PORTx_PCRn register.
• Minimize loading on the I2C SDA and SCL pins to ensure fastest rise times for the
SCL line to avoid clock stretching.
• Use smaller pull up resistors on SDA and SCL to reduce the RC time constant.
Table 89. I
2
C 1Mbit/s timing
Characteristic Symbol Minimum Maximum Unit
SCL Clock Frequency f
SCL
0 1 MHz
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
t
HD
; STA 0.26 — µs
LOW period of the SCL clock t
LOW
0.5 — µs
HIGH period of the SCL clock t
HIGH
0.26 — µs
Set-up time for a repeated START condition t
SU
; STA 0.26 — µs
Data hold time for I
2
C bus devices t
HD
; DAT 0 — µs
Data set-up time t
SU
; DAT 50 — ns
Rise time of SDA and SCL signals t
r
20 +0.1C
b
120 ns
Table continues on the next page...
Electrical characteristics
122
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
NXP Semiconductors