Datasheet

Table 87. Slave mode DSPI timing (full voltage range)
Num Description Min. Max. Unit
Operating voltage 1.71 3.6 V
Frequency of operation — 7.5 MHz
DS9 DSPI_SCK input cycle time 8 x t
BUS
— ns
DS10 DSPI_SCK input high/low time (t
SCK
/2) - 4 (t
SCK/2)
+ 4 ns
DS11 DSPI_SCK to DSPI_SOUT valid — 23.1 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns
DS13 DSPI_SIN to DSPI_SCK input setup 2.6 — ns
DS14 DSPI_SCK to DSPI_SIN input hold 7.0 — ns
DS15 DSPI_SS active to DSPI_SOUT driven — 13.0 ns
DS16 DSPI_SS inactive to DSPI_SOUT not driven — 13.0 ns
First data Last data
First data Data Last data
Data
DS15
DS10 DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 43. DSPI classic SPI timing — slave mode
5.4.7.5
Inter-Integrated Circuit Interface (I2C) timing
Table 88. I2C timing
Characteristic Symbol Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency f
SCL
0 100 0 400
1
kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
t
HD
; STA 4 — 0.6 — µs
LOW period of the SCL clock t
LOW
4.7 — 1.25 — µs
HIGH period of the SCL clock t
HIGH
4 — 0.6 — µs
Set-up time for a repeated START
condition
t
SU
; STA 4.7 — 0.6 — µs
Data hold time for I
2
C bus devices t
HD
; DAT 0
2
3.45
3
0
4
0.9
2
µs
Table continues on the next page...
Electrical characteristics
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
121
NXP Semiconductors