Datasheet

5.4.7.4 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 86. Master mode DSPI timing (full voltage range)
Num Description Min. Max. Unit Notes
Operating voltage 1.71 3.6 V 1
Frequency of operation — 15 MHz
DS1 DSPI_SCK output cycle time 4 x t
BUS
— ns
DS2 DSPI_SCK output high/low time (t
SCK
/2) - 4 (t
SCK/2)
+ 4 ns
DS3 DSPI_PCSn valid to DSPI_SCK delay (t
BUS
x 2) −
4
— ns 2
DS4 DSPI_SCK to DSPI_PCSn invalid delay (t
BUS
x 2) −
4
— ns 3
DS5 DSPI_SCK to DSPI_SOUT valid — 16 ns
DS6 DSPI_SCK to DSPI_SOUT invalid 1.0 — ns
DS7 DSPI_SIN to DSPI_SCK input setup 19.1 — ns
DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DS3 DS4
DS1
DS2
DS7
DS8
First data
Last data
DS5
First data Data Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 42. DSPI classic SPI timing — master mode
Electrical characteristics
120
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
NXP Semiconductors