Datasheet

The phase-locked loop (PLL) can generate up to 144 MHz high speed, low jitter clock
with 8–16 MHz internal or external reference clock. The PLL can be used as the system
clock or clock source for other on-chip modules.
For more details on the clock operations and configurations, see Reference Manual.
32 kHz IRC
PLL
FLL
MCGOUTCLK
MCGPLLCLK
MCG
MCGFLLCLK
OUTDIV1
Core / system clocks
4 MHz IRC
OUTDIV5
QSPI bus interface clock
OUTDIV2
Bus clock
RTC oscillator
EXTAL32
XTAL32
EXTAL0
XTAL0
System oscillator
SIM
FRDIV
MCGIRCLK
ERCLK32K
OSC32KCLK
XTAL_CLK
MCGFFCLK
OSCERCLK
OSC
logic
OSC logic
Clock options for
some peripherals
(see note)
MCGFLLCLK/
IRC48MCLK/
MCGPLLCLK/
Note: See subsequent sections for details on where these clocks are used.
PMC logic
PMC
LPO
OSCCLK
CG
CG
CG
CG
CG
CG — Clock gate
RTC_CLKOUT
Clock options for some
peripherals (see note)
FCRDIV
1Hz
32.768 kHz
PRDIV
IRC48M
IRC48M logic
IRC48MCLK
DIV
DIV_OSCERCLK
IRC48MCLK
OUTDIV4
Flash clock
CG
Figure 3. Clocking diagram
In order to provide flexibility, many peripherals can select from multiple clock sources
for operation. This enables the peripheral to select a clock that will always be available
during operation in various operational modes.
Overview
12
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
NXP Semiconductors