Datasheet

DS3 DS4
DS1
DS2
DS7
DS8
First data
Last data
DS5
First data Data Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 40. DSPI classic SPI timing — master mode
Table 85. Slave mode DSPI timing (limited voltage range)
Num Description Min. Max. Unit
Operating voltage 2.7 3.6 V
Frequency of operation — 15
1
MHz
DS9 DSPI_SCK input cycle time 4 x t
BUS
— ns
DS10 DSPI_SCK input high/low time (t
SCK
/2) − 2 (t
SCK
/2) + 2 ns
DS11 DSPI_SCK to DSPI_SOUT valid — 23.0 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns
DS13 DSPI_SIN to DSPI_SCK input setup 2.7 — ns
DS14 DSPI_SCK to DSPI_SIN input hold 7.0 — ns
DS15 DSPI_SS active to DSPI_SOUT driven — 13 ns
DS16 DSPI_SS inactive to DSPI_SOUT not driven — 13 ns
1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with
continuous CS and SCK, there is a constraint that SPI clock should not be greater than 1/6 of system clock, for
example, when system clock is 60MHz, SPI clock should not be greater than 10MHz.
First data Last data
First data Data Last data
Data
DS15
DS10 DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 41. DSPI classic SPI timing — slave mode
Electrical characteristics
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
119
NXP Semiconductors