Datasheet

NOTE
The MCGPLLCLK meets the USB jitter and signaling rate
specifications for certification with the use of an external
clock/crystal for both Device and Host modes.
The IRC48M meets the USB jitter and signaling rate
specifications for certification in Device mode when the USB
clock recovery mode is enabled. It does not meet the USB
signaling rate specifications for certification in Host mode
operation.
5.4.7.3 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to
the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 84. Master mode DSPI timing (limited voltage range)
Num Description Min. Max. Unit Notes
Operating voltage 2.7 3.6 V
Frequency of operation — 24 MHz 1
DS1 DSPI_SCK output cycle time 2 x t
BUS
— ns
DS2 DSPI_SCK output high/low time (t
SCK
/2) − 2 (t
SCK
/2) + 2 ns
DS3 DSPI_PCSn valid to DSPI_SCK delay (t
BUS
x 2) −
2
— ns 2
DS4 DSPI_SCK to DSPI_PCSn invalid delay (t
BUS
x 2) −
2
— ns 3
DS5 DSPI_SCK to DSPI_SOUT valid — 15.0 ns
DS6 DSPI_SCK to DSPI_SOUT invalid 1.0 — ns
DS7 DSPI_SIN to DSPI_SCK input setup 15.8 — ns
DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns
1. The SPI can run at a maximum frequency of 24 MHz serial clocks on PORTE interface, and up to 18 MHz on other
PORT interfaces
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Electrical characteristics
118
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
NXP Semiconductors