Datasheet

EMVSIMn_VCCEN
EMVSIMn_CLK
EMVSIMn_IO
2
T0
1
RESPONSE
EMVSIMn_RST
T1
3
3
Figure 38. Active-Low-Reset Smart Card Reset Sequence
The following table defines the general timing requirements for the EMVSIM
interface..
Table 82. Timing Specifications, Internal Reset Card Reset Sequence
Ref No Min Max Units
1 — 200 EMVSIMx_CLK clock cycles
2 400 40,000 EMVSIMx_CLK clock cycles
3 40,000 — EMVSIMx_CLK clock cycles
5.4.7.1.2 EMVSIM Power-Down Sequence
Following figure shows the EMV SIM interface power-down AC timing diagram.Table
83 table shows the timing requirements for parameters (SI7–SI10) shown in the figure.
The power-down sequence for the EMV SIM interface is as follows:
• EMVSIMn_SIMPD port detects the removal of the Smart Card
• EMVSIMn_RST is negated
• EMVSIMn_CLK is negated
• EMVSIM_IO is negated
• EMVSIMx_VCCENy is negated
Each of the above steps requires one RTC CLK period (usually 32 kHz). Power-down
may be initiated by a Smart card removal detection; or it may be launched by the
processor.
Electrical characteristics
116
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
NXP Semiconductors