Datasheet

EMVSIMn_CLK

EMVSIMn_IO

RESPONSE

EMVSIMn_VCCEN

Figure 37. Internal Reset Card Reset Sequence

The following table defines the general timing requirements for the SIM interface.

Table 81. Timing Specifications, Internal Reset Card Reset Sequence

Ref Min Max Units

1 — 200 EMVSIMx_CLK

clock cycles

2 400 40,000 EMVSIMx_CLK

clock cycles

5.4.7.1.1.2 Smart Cards with Active Low Reset

Following figure shows the reset sequence for Smart cards with active low reset. The

reset sequence comprises the following steps::

• After power-up, the clock signal is enabled on EMVSIMn_CLK (time T0)

• After 200 clock cycles, EMVSIMn_IO must be asserted.

• EMVSIMn_RST must remain low for at least 40,000 clock cycles after T0 (no

response is to be received on RX during those 40,000 clock cycles)

• EMVSIMn_RST is asserted (at time T1)

• EMVSIMn_RST must remain asserted for at least 40,000 clock cycles after T1,

and a response must be received on EMVSIMn_IO between 400 and 40,000 clock

cycles after T1.

Electrical characteristics

Kinetis KL82 Microcontroller, Rev. 3, 08/2016

115

NXP Semiconductors