Datasheet

The following table defines the general timing requirements for the EMV SIM
interface.
Table 80. Timing Specifications, High Drive Strength
ID Parameter Symbol Min Max Unit
SI
1
EMV SIM clock frequency (EMVSIMn_CLK)
1
S
freq
0.01 25 MHz
SI
2
EMV SIM clock rise time (EMVSIMn_CLK)
2
S
rise
— 0.09 × (1/Sfreq) ns
SI
3
EMV SIM clock fall time (EMVSIMn_CLK)
2
S
fall
— 0.09 × (1/Sfreq) ns
SI
4
EMV SIM input transition time (EMVSIMn_IO,
EMVSIMn_PD)
S
tran
20 25 ns
Si
5
EMV SIM I/O rise time / fall time (EMVSIMn_IO)
3
Tr/Tf — 1 ns
Si
6
EMV SIM RST rise time / fall time (EMVSIMn_RST)
4
Tr/Tf — 1 ns
1. 50% duty cycle clock,
2. With C = 50 pF
3. With Cin = 30 pF, Cout = 30 pF,
4. With Cin = 30 pF,
5.4.7.1.1 EMV SIM Reset Sequences
Smart cards may have internal reset, or active low reset. The following subset describes
the reset sequences in these two cases.
5.4.7.1.1.1
Smart Cards with Internal Reset
Following figure shows the reset sequence for Smart cards with internal reset. The reset
sequence comprises the following steps:
• After power-up, the clock signal is enabled on EMVSIMn_CLK (time T0)
• After 200 clock cycles, EMVSIMn_IO must be asserted.
• The card must send a response on EMVSIMn_IO acknowledging the reset between
400–40000 clock cycles after T0.
Electrical characteristics
114
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
NXP Semiconductors