Datasheet

Table 68. Flash command timing specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
t
vfykey
Verify Backdoor Access Key execution time — — 30 μs 1
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
5.4.3.2.3 Flash high voltage current behaviors
Table 69. Flash high voltage current behaviors
Symbol Description Min. Typ. Max. Unit
I
DD_PGM
Average current adder during high voltage
flash programming operation
— 2.5 6.0 mA
I
DD_ERS
Average current adder during high voltage
flash erase operation
— 1.5 4.0 mA
5.4.3.2.4 Reliability specifications
Table 70. NVM reliability specifications
Symbol Description Min. Typ.
1
Max. Unit Notes
Program Flash
t
nvmretp10k
Data retention after up to 10 K cycles 5 50 — years —
t
nvmretp1k
Data retention after up to 1 K cycles 20 100 — years —
n
nvmcycp
Cycling endurance 10 K 50 K — cycles 2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ T
j
≤ 125 °C.
5.4.4 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
5.4.5
Analog
5.4.5.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 1 and Table 72 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
Electrical characteristics
Kinetis KL82 Microcontroller, Rev. 3, 08/2016
101
NXP Semiconductors